Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
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HPS NAND Timing Characteristics

Table 90.  HPS NAND ONFI 1.0 Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Max Unit
TWP 120 Write enable pulse width 10 ns
TWH 120 Write enable hold time 7 ns
TRP 120 Read enable pulse width 10 ns
TREH 120 Read enable hold time 7 ns
TCLS 120 Command latch enable to write enable setup time 10 ns
TCLH 120 Command latch enable to write enable hold time 5 ns
TCS 120 Chip enable to write enable setup time 15 ns
TCH 120 Chip enable to write enable hold time 5 ns
TALS 120 Address latch enable to write enable setup time 10 ns
TALH 120 Address latch enable to write enable hold time 5 ns
TDS 120 Data to write enable setup time 7 ns
TDH 120 Data to write enable hold time 5 ns
TWB 120 Write enable high to R/B low 200 ns
TCEA Chip enable to data access time 100 ns
TREA Read enable to data access time 40 ns
TRHZ Read enable to data high impedance 200 ns
TRR Ready to read enable low 20 ns
Figure 17. NAND Command Latch Timing Diagram
Figure 18. NAND Address Latch Timing Diagram
Figure 19. NAND Data Output Cycle Timing Diagram
Figure 20. NAND Data Input Cycle Timing Diagram
Figure 21. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 22. NAND Read Status Timing Diagram
Figure 23. NAND Read Status Enhanced Timing Diagram
120 This timing is software programmable. Refer to the related information for more information about software-programmable timing in the NAND flash controller.