Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 2/20/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

HPS NAND Timing Characteristics

Table 90.  HPS NAND ONFI 1.0 Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Max Unit
TWP 117 Write enable pulse width 10 — ns
TWH 117 Write enable hold time 7 — ns
TRP 117 Read enable pulse width 10 — ns
TREH 117 Read enable hold time 7 — ns
TCLS 117 Command latch enable to write enable setup time 10 — ns
TCLH 117 Command latch enable to write enable hold time 5 — ns
TCS 117 Chip enable to write enable setup time 15 — ns
TCH 117 Chip enable to write enable hold time 5 — ns
TALS 117 Address latch enable to write enable setup time 10 — ns
TALH 117 Address latch enable to write enable hold time 5 — ns
TDS 117 Data to write enable setup time 7 — ns
TDH 117 Data to write enable hold time 5 — ns
TWB 117 Write enable high to R/B low — 200 ns
TCEA Chip enable to data access time — 100 ns
TREA Read enable to data access time — 40 ns
TRHZ Read enable to data high impedance — 200 ns
TRR Ready to read enable low 20 — ns
Figure 16. NAND Command Latch Timing Diagram
Figure 17. NAND Address Latch Timing Diagram
Figure 18. NAND Data Output Cycle Timing Diagram
Figure 19. NAND Data Input Cycle Timing Diagram
Figure 20. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 21. NAND Read Status Timing Diagram
Figure 22. NAND Read Status Enhanced Timing Diagram
Related Information
117 This timing is software programmable. Refer to the related information for more information about software-programmable timing in the NAND flash controller.
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