|Differential I/O Standards
|Receiver Input Waveforms
Transmitter Output Waveforms
|I/O PLL input clock frequency.
|LVDS SERDES block—maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA.
|LVDS SERDES block—maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA.
|J (SERDES factor)
|LVDS SERDES block—deserialization factor (width of parallel data bus).
|JTAG Timing Specifications
|JTAG Timing Specifications:
|Receiver differential input discrete resistor (external to the device).
|Sampling window (SW)
|Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown:
|Single-ended voltage referenced I/O standard
|The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
|High-speed receiver/transmitter input and output clock period.
|The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table).
|LVDS SERDES block—duty cycle on high-speed transmitter output clock.
|Signal high-to-low transition time (80–20%).
|Cycle-to-cycle jitter tolerance on the PLL clock input.
|Period jitter on the GPIO driven by a PLL.
|Period jitter on the dedicated clock output driven by a PLL.
|Signal low-to-high transition time (20–80%).
|Timing Unit Interval (TUI)
|The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
|DC Common mode input voltage.
|Input Common mode voltage—the common mode of the differential signal at the receiver.
|VCM(DC) DC Common mode input voltage.
|Input differential voltage swing—the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver.
|AC differential input voltage—minimum AC input differential voltage required for switching.
|DC differential input voltage—minimum DC input differential voltage required for switching.
|Voltage input high—the minimum positive voltage applied to the input which is accepted by the device as a logic high.
|High-level AC input voltage.
|High-level DC input voltage.
|Voltage input low—the maximum positive voltage applied to the input which is accepted by the device as a logic low.
|Low-level AC input voltage.
|Low-level DC input voltage.
|Output Common mode voltage—the common mode of the differential signal at the transmitter.
|Output differential voltage swing—the difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter.
|Differential input voltage.
|Output differential cross point voltage.
|VIX Input differential cross point voltage.
|LVDS SERDES block—Clock Boost Factor.