Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Download
ID 683301
Date 2/20/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

HPS I2C Timing Characteristics

Table 89.  HPS I2C Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 — 2.5 — μs
Tclk_jitter I2C clock output jitter — 2 — 2 %
THIGH 106 SCL high period 4107 — 0.6108 — μs
TLOW 109 SCL low period 4.7110 — 1.3111 — μs
TSU;DAT Setup time for serial data line (SDA) data to SCL 0.25 — 0.1 — μs
THD;DAT 112 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
TVD;DAT and TVD;ACK 113 SCL to SDA output data delay — 3.45114 — 0.9115 μs
TSU;STA Setup time for a repeated start condition 4.7 — 0.6 — μs
THD;STA Hold time for a repeated start condition 4 — 0.6 — μs
TSU;STO Setup time for a stop condition 4 — 0.6 — μs
TBUF SDA high pulse duration between STOP and START 4.7 — 1.3 — μs
Tscl:r 116 SCL rise time — 1,000 20 300 ns
Tscl:f 116 SCL fall time — 300 6.54 300 ns
Tsda:r 116 SDA rise time — 1,000 20 300 ns
Tsda:f 116 SDA fall time — 300 6.54 300 ns
Figure 15. I2C Timing Diagram
Related Information
106 You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
107 The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the related information for the SCL_High_time equation.
108 The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the related information for the SCL_High_time equation.
109 You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
110 The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the related information for the SCL_Low_time equation.
111 The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the related information for the SCL_Low_time equation.
112 THD;DAT is affected by the rise and fall time.
113 TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
114 Use maximum SDA_HOLD = 240 to be within the specification.
115 Use maximum SDA_HOLD = 60 to be within the specification.
116 Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value, and total capacitance on the transmission line.
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message