Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

P-Tile Receiver Specifications

Table 55.  P-Tile Receiver Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O standards PCIe* High Speed Differential I/O
Peak-to-peak differential input voltage VID (diff p-p) PCIe* 2.5 GT/s71 17572 1,200 mV
PCIe* 5.0 GT/s71 10072 1,200 mV
PCIe* 8.0 GT/s 2572 73 mV
PCIe* 16.0 GT/s 1572 73 mV
Differential on-chip termination resistors 80 120
RESREF74 167.3 169 170.7
RREF 2.772 2.8 2.828 kΩ
71 Voltage shown for PCIe* 2.5 GT/s and 5.0 GT/s are at the package pins (TP2).
72 For PCIe* at 2.5 GT/s and 5 GT/s, the VID is measured at TP2, which is the accessible test point at the device under test. For PCIe* 8.0 GT/s and 16.0 GT/s, the VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
73 The maximum eye height value depends on the transmitter launch voltage maximum value. Refer to the PCIe* Express Base Specification Rev. 4.0 for the generator (TX) launch voltage value.
74 Connecting RESREF at 169 Ω calibrates PCIe* channel on-chip termination to 85 Ω.