Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
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R-Tile Transceiver Reference Clock Specifications

Table 59.  R-Tile Reference Clock Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O standards PCIe* HCSL
CXL HCSL
Refclk frequency for devices that support 32.0 GT/s77 PCIe* 99.99 100 100.01 MHz
CXL 99.99 100 100.01 MHz
Rising edge rate78 PCIe* 0.6 4 V/ns
CXL 0.6 4 V/ns
Falling edge rate78 PCIe* 0.6 4 V/ns
CXL 0.6 4 V/ns
Duty cycle PCIe* 40 60 %
CXL 40 60 %
Absolute VMAX PCIe* 1.15 V
CXL 1.15 V
Absolute VMIN PCIe* –0.3 V
CXL –0.3 V
Peak-to-peak differential input voltage PCIe* 300 1,450 mV
CXL 300 1,450 mV
Vcross PCIe* 250 550 mV
CXL 250 550 mV
Cycle-to-cycle jitter (TCCJITTER)79 PCIe* 150 ps
CXL 150 ps
Spread-spectrum modulating clock frequency PCIe* 30 33 kHz
CXL 30 33 kHz
SSC deviation for devices that support 32.0 GT/s and SRIS when operating in SRIS mode at all speeds PCIe* –0.3 0 %
CXL –0.3 0 %
TSSC-MAX-PERIOD-SLEW Max SSC df/dt for PCIe* 1,250 ppm/µs
Max SSC df/dt for CXL 1,250 ppm/µs
77 This number is with spread-spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications in Section 8.6 Refclk Specifications of PCI Express* Base Specification Revision 5.0 Version 1.0.
78 Measured from –150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential zero crossing.
79 For common reference clock architecture, you must meet the jitter limit specified in Section 8.6 Refclk Specifications of PCI Express* Base Specification Revision 5.0 Version 1.0.