Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
Public
Document Table of Contents

HPS SD/MMC Timing Characteristics

Table 81.  HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements

These timings apply to SD, MMC, and embedded MMC (eMMC) cards operating at 1.8 V.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit
Tsdmmc_cclk SDMMC_CCLK clock period (Identification mode) 2,500 ns
SDMMC_CCLK clock period (SDR12) 40 ns
SDMMC_CCLK clock period (SDR25) 20 ns
Tdutycycle SDMMC_CCLK duty cycle 45 50 55 %
Tsdmmc_cclk_jitter SDMMC_CCLK output jitter 2 %
Tsdmmc_clk Internal reference clock before division by 4 5 ns
Td SDMMC_CMD/SDMMC_DATA[7:0] output delay104 –0.5 + Tsdmmc_clk × drvsel/2 2.5 + (Tsdmmc_clk × drvsel/2) ns
Tsu SDMMC_CMD/SDMMC_DATA[7:0] input setup105 6 – (Tsdmmc_clk × smplsel/2) ns
Th SDMMC_CMD/SDMMC_DATA[7:0] input hold105 0.5 + (Tsdmmc_clk × smplsel/2) ns
None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.
Note: SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC interface.
Figure 9. SD/MMC Timing Diagram
104 When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the output delay time is 7.5 to 10.5 ns.
105 When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the setup time is 1 ns and the hold time is 5.5 ns.