Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 7/08/2024
Public
Document Table of Contents

HPS Clock Performance

Table 74.  Maximum HPS Clock Frequencies For specification status, see the Data Sheet Status table
Performance VCCL_HPS (V) MPU Frequency (MHz) L3 Frequency (MHz) (l3_main_free_clk) MPFE Frequency (MHz) Rate DDR Clock (MHz) DDR (Mb/s per pin)
–1 speed grade Fixed: 0.95 1,500 400 400 Quarter 1,600 3,200
667 Half 1,333 2,666
SmartVID 1,350 400 400 Quarter 1,600 3,200
667 Half 1,333 2,666
–2 speed grade SmartVID 1,200 400 334 Quarter 1,333 2,666
600 Half 1,200 2,400
–3 speed grade SmartVID 1,000 400 300 Quarter 1,200 2,400
534 Half 1,067 2,133
–4 speed grade Fixed: 0.8 1,000 400 267 Quarter 1,067 2,133
467 Half 933 1,866