Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Recommended Operating Conditions

Table 7.  Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table
Symbol Description Condition Minimum5 Typical Maximum5 Unit
VCC Core voltage power supply SmartVID6 : –1V, –2V, –3V, –3E, –4X (Typical) – 3% 0.70 – 0.907 (Typical) + 3% V
Fixed voltage: –4F 0.776 0.8 0.824 V
VCCP Periphery circuitry power supply SmartVID6: –1V, –2V, –3V, –3E, –4X (Typical) – 3% 0.70 – 0.907 (Typical) + 3% V
Fixed voltage: –4F 0.776 0.8 0.824 V
VCCPT Power supply for I/O PLL and I/O pre-driver — 1.71 1.8 1.89 V
VCCRCORE CRAM power supply — 1.14 1.2 1.26 V
VCCH Advanced interface bus (AIB) power supply Devices with E-Tile and P-Tile 0.87 0.9 0.93 V
Devices with R-Tile and F-Tile 0.776 0.8 0.824 V
Devices with F-Tile only 0.776 0.8 0.824 V
VCCH_SDM SDM block transceiver digital power sense Devices with E-Tile and P-Tile 0.87 0.9 0.93 V
Devices with R-Tile and F-Tile 0.87 0.9 0.93 V
Devices with F-Tile only 0.776 0.8 0.824 V
VCCIO_PIO_SDM 8 SDM block I/O bank power sense of Bank 3A 1.5 V 1.455 1.5 1.545 V
1.2 V 1.14 1.2 1.26 V
VCCIO_SDM SDM block configuration pins power supply — 1.71 1.8 1.89 V
VCCL_SDM SDM block core voltage power supply — 0.776 0.8 0.824 V
VCCFUSEWR_SDM SDM block fuse writing power supply — 1.75 1.8 1.85 V
VCCPLLDIG_SDM SDM block PLL digital power supply — 0.776 0.8 0.824 V
VCCPLL_SDM SDM block PLL analog power supply — 1.71 1.8 1.89 V
VCCBAT 9 Battery back-up power supply (For design security volatile key register) — 1 — 1.8 V
IBAT 10 Battery back-up power supply (For design security volatile key register) VCCBAT = 1.2 V — — 200 nA
VCCADC ADC voltage sensor power supply — 1.71 1.8 1.89 V
VCCIO_PIO I/O bank power supply 1.5 V 1.455 1.5 1.545 V
1.2 V 1.14 1.2 1.26 V
VCCA_PLL I/O clock network power supply — 1.14 1.2 1.26 V
VI 11 DC input voltage VCCIO_PIO = 1.2 V –0.3 — VCCIO_PIO + 0.3 V
VCCIO_PIO = 1.5 V 0 — 1.7 V
VCCIO_SDM = 1.8 V –0.3 — VCCIO_SDM + 0.3 V
VCCIO_HPS = 1.8 V –0.3 — VCCIO_HPS + 0.3 V
VO Output voltage VCCIO_PIO = 1.2 V, 1.5 V 0 — VCCIO_PIO V
VCCIO_SDM = 1.8 V 0 — VCCIO_SDM V
VCCIO_HPS = 1.8 V 0 — VCCIO_HPS V
TJ Operating junction temperature Extended 0 — 100 °C
Industrial –4012 — 100 °C
tRAMP 13 14 Power supply ramp time Standard POR 200 μs — 100 ms —
5 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.
6 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
7 The typical value is based on the SmartVID programmed value.
8 Must be powered up with the same voltage level as VCCIO_PIO_3A. Must be supplied at 1.2 V when using Avalon®-ST ×16/×32 configuration schemes.
9 Power up VCCBAT with a non-volatile battery power source when using the device security AES BBRAM key. When not using the AES BBRAM key, tie this pin to ground.
10 At 25 °C. This supply current specification does not apply to –E4F speed grade and power option device.
11 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
12 E-Tile supports an operating temperature range of –40°C to 100°C. However, the E-Tile transceivers may experience a higher error rate from –40°C to –20°C because of the calibration procedure when starting at a low temperature. Therefore, the recommended operating temperature range for E-Tile protocol-compliant transceiver links is –20°C to 100°C. The maximum temperature ramp rate is 2°C per minute.
13 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
14 To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating conditions.
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