Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
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DPA Lock Time Specifications

Table 41.  DPA Lock Time Specifications

The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1- to-0 transition.

For specification status, see the Data Sheet Status table

Standard Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions59 Maximum Data Transition
SPI-4 00000000001111111111 2 128 768
Parallel Rapid I/O 00001111 2 128 768
10010000 4 64 768
Miscellaneous 10101010 8 32 768
01010101 8 32 768
59 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.