Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

DPA Lock Time Specifications

Table 41.  DPA Lock Time Specifications

The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1- to-0 transition.

For specification status, see the Data Sheet Status table

Standard Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions59 Maximum Data Transition
SPI-4 00000000001111111111 2 128 768
Parallel Rapid I/O 00001111 2 128 768
10010000 4 64 768
Miscellaneous 10101010 8 32 768
01010101 8 32 768
59 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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