Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

1. Overview of the Agilex™ 5 FPGAs and SoCs

The Agilex™ 5 FPGA product family extends the innovations of the Agilex™ FPGA portfolio to midrange FPGA applications. The Agilex™ 5 FPGAs and SoCs serve a broad range of applications that require high performance, lower power consumption, smaller form factor, and lower logic densities.
  • First enhanced DSP with AI Tensor block in the industry—delivers high-efficiency artificial intelligence (AI) and digital signal processing (DSP)
  • First asymmetric applications processor system in the FPGA industry—a combination of a dual-core Arm* Cortex* -A76 and a dual-core Arm* Cortex* -A55 processors enables you to optimize the performance and power efficiency of processing workloads
  • Monolithic die architecture—provides higher system integration and lower power with smaller form factor packages
  • Advanced connectivity features:
    • High-speed GTS transceivers up to 28.1 Gbps
    • PCI Express* ( PCIe* ) 4.0 ×8 support
    • DDR external memory interface up to 4,000 Mbps DDR5
    • General purpose I/Os supporting voltages from 1.0 V to 3.3 V

The Agilex™ 5 FPGA product family delivers on average 50% higher fabric performance and up to 42% lower total power consumption compared to previous generation Intel® FPGAs. To achieve this improvement, the product family leverages these key innovations and techniques:

  • Advanced Intel® 7 technology
  • Second generation Hyperflex® FPGA architecture
  • High level of system integration
  • SmartVID and fixed low core voltage device options
  • Power islands, power gating, and other power reduction techniques

These capabilities and advanced features make the Agilex™ 5 FPGA product family ideal for midrange FPGA applications across the edge and core. The applications span across many segments including wireless and wireline communications, video and broadcast equipments, industrial, test and measurement, medical electronics, data centers, and defense.

Note: The information contained in this document is preliminary and subject to change.