Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs

Intel built the partial reconfiguration process on top of the proven incremental compile design flow in the Quartus® Prime design software. With partial reconfiguration, you can reconfigure parts of the FPGA while other sections continue to run. In systems with critical uptime requirement, you can update or adjust functions without disrupting service provision.

Apart from lowering power usage and cost, partial configuration effectively increases the logic density. Instead of placing all functions in the FPGA from the start, you can store functions that do not have to operate simultaneously in external memory. You can load these function into the FPGA when needed. Using this technique, you can run multiple applications on a single FPGA and reduce the requirements for FPGA size, board space, and power.

With dynamic reconfiguration, Agilex™ 5 FPGAs and SoCs can dynamically change data rates, protocols, and analog settings of a transceiver channel without affecting data transfer on adjacent transceiver channels. This capability is ideal for applications that require on-the-fly multi-protocol or multi-rate support.

You can dynamically reconfigure both the PMA and PCS blocks within the transceiver. You can also use dynamic reconfiguration together with partial reconfiguration to partially reconfigure the FPGA core and transceivers simultaneously.