Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

1.3. Agilex™ 5 FPGAs and SoCs Summary of Features

The Agilex™ 5 FPGAs and SoCs share the same high performance core fabric and common features.
Table 2.   Feature Summary
Feature Description
Packaging
  • Multiple devices with identical package footprints allows seamless migration across different device densities
  • Variable Pitch BGA (VPBGA) package design with minimum ball pitch of 0.65 mm 4 for smaller package form factor and to help reduce the number of PCB layers
E-Series 0.5 mm ball pitch package option for small form-factor with more I/O counts
High performance core fabric
  • Second Generation Hyperflex® core architecture with Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks
  • Enhanced adaptive logic module (ALM)
  • Improved multi-track routing architecture reduces congestion and improves compile times
  • Hierarchical core clocking architecture with programmable clock tree synthesis
  • Fine-grained partial reconfiguration
Internal memory blocks
  • Multi-level on-chip memory hierarchy
  • M20K—20 kilobits with hard error correction code (ECC) support
  • MLAB—640-bit distributed LUTRAM
Variable precision DSP blocks
  • Variable precision DSP blocks with hard IEEE 754-compliant floating-point units, including support for:
    • Single-precision FP32 (32-bit arithmetic)
    • Half-precision FP16 (16-bit arithmetic) and FP19 (19-bit arithmetic) floating point modes
    • Tensor floating point FP19 floating point modes
    • BFLOAT16 floating-point format
  • High-performance AI Tensor blocks:
    • Enables high-performance compute density of FPGA fabric Tera Operations Per Second (TOPS)
    • Up to 57 INT8 TOPS for AI workloads
    • Hardware programmable for AI with customized workloads
    • Supports push-button flow from industry standard frameworks, such as TensorFlow* , to FPGA bitstream
  • Every DSP block supports INT16 complex multiplication mode
  • Supports signal processing with precision ranging from 9×9 up to 54×54
  • Native 27×27, 18×19, and 9×9 multiplication modes
  • 64-bit accumulator and cascade for systolic 200 GbE finite impulse responses (FIRs)
  • Internal coefficient memory banks
  • Pre-adder/subtractor improves efficiency
  • 2× additional pipeline register increases performance and reduces power consumption
Core clock networks
  • Programmable clock tree synthesis—backwards compatible with global, regional and peripheral clock networks
  • Synthesize clocks where needed only—minimizes dynamic power
  • 800 MHz LVDS interface clocking—supports 1,600 Mbps LVDS interface through the 1.3 V TDS standard compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
D-Series 2,000 MHz external memory interface clocking, supports 4,000 Mbps DDR5 interface
E-Series Device Group A 1,800 MHz external memory interface clocking, supports 3,600 Mbps DDR5 interface
Device Group B 1,200 MHz external memory interface clocking, supports 2,400 Mbps DDR4 interface
General purpose I/Os General
  • 1.6 Gbps 1.3 V TDS standard compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
  • 1.0 V, 1.05 V, 1.1 V, and 1.2 V single-ended LVCMOS interfacing
  • 1.8 V, 2.5 V, and 3.3 V single-ended LVCMOS/LVTTL I/O
  • On-chip termination (OCT)

D-Series

 Over 400 total GPIOs available
E-Series Over 500 total GPIOs available

External memory interface

(Hard IP)

D-Series
  • 2,000 MHz (4,000 Mbps) DDR5 external memory interface
  • 2,133 MHz (4,267 Mbps) LPDDR5 external memory interface
  • 1,600 MHz (3,200 Mbps) DDR4 external memory interface
  • 2,133 MHz (4,267 Mbps) LPDDR4/4X external memory interface
E-Series Device Group A
  • 1,800 MHz (3,600 Mbps) DDR5 external memory interface
  • 1,867 MHz (3,733 Mbps) LPDDR5 external memory interface
  • 1,333 MHz (2,667 Mbps) DDR4 external memory interface
  • 1,867 MHz (3,733 Mbps) LPDDR4 external memory interface
Device Group B
  • 1,200 MHz (2,400 Mbps) DDR4 external memory interface
  • 1,333 MHz (2,667 Mbps) LPDDR4 external memory interface
  • 1,200 MHz (2,400 Mbps) LPDDR5 external memory interface
MIPI* D-Series MIPI* D-PHY* v2.5 at up to 3.5 Gbps 5 per lane
E-Series Device Group A MIPI* D-PHY* v2.5 at up to 3.5 Gbps 5 per lane
Device Group B MIPI* D-PHY* v2.5 at up to 2.5 Gbps 6 per lane
Phase locked loops (PLL) I/O PLL
  • Integer PLLs adjacent to general purpose I/Os
  • Precision frequency synthesis
  • Clock delay compensation
  • Zero-delay buffering
  • Support external memory and LVDS-compatible interface

Transmit PLLs

(TX PLLs)
  • Precise fractional synthesis
  • Ultra low jitter with LC tank-based PLL
  • Supports transceiver interfaces
System PLL
  • One System PLL per GTS transceiver bank
  • Integer mode
  • Precision frequency synthesis
  • Supports transceiver-to-fabric interface
  • You can repurpose the System PLL for core usage if it is not used by the GTS transceiver
Memory controller support Multiple hard IP instantiations in each device
D-Series
  • DDR4 hard memory controller
  • LPDDR4/4X hard memory controller
  • DDR5 hard memory controller
  • LPDDR5 hard memory controller
E-Series Device Group A
  • DDR4 hard memory controller
  • LPDDR4 hard memory controller
  • DDR5 hard memory controller
  • LPDDR5 hard memory controller
Device Group B
  • DDR4 hard memory controller
  • LPDDR4 hard memory controller
  • LPDDR5 hard memory controller
Transceivers PCIe* PCIe* rates up to PCIe* 4.0, 16 Gbps NRZ
Networking
  • Insertion loss compliant to 802.3bj and CEI 25G-LR standards
  • Oversampling capability for data rates below 1 Gbps
  • SFP+ optical module support
  • Adaptive linear and decision feedback equalization
  • Transmit pre-emphasis and de-emphasis
  • Dynamic reconfiguration of individual GTS transceiver channels
  • On-chip instrumentation ( Quartus® Prime Eye Viewer with non-destructive eye height and destructive eye width margining)
D-Series Continuous operating range of 1 Gbps to 28.1 Gbps NRZ
E-Series Device Group A Continuous operating range of 1 Gbps to 28.1 Gbps NRZ
Device Group B Continuous operating range of 1 Gbps to 17.16 Gbps NRZ
Transceiver hard IP PCIe*
  • Multiple hard IP instantiations in each device
  • TLP bypass feature
  • Single-root I/O virtualization (SR-IOV)
  • Precise time management
D-Series
  • Up to PCIe* 4.0 ×8 EP and RP
  • Port bifurcation support: 4×8 root port or endpoint, or (4×4)+(4×4) root port or endpoint
E-Series
  • Up to PCIe* 4.0 ×4 EP and RP
  • 6 × 4 endpoint or root ports
Other protocols
  • CPRI and fibre channel
  • CR/KR (AN/LT)
  • 1588 PTP
  • MAC, PCS, and FEC bypass options
D-Series Ethernet IP configuration: 16× 10 or 25 GbE MAC, PCS, and FEC
E-Series Device Group A Ethernet IP configuration: 6 × 10 or 25 GbE MAC, PCS, and FEC
Device Group B Ethernet IP configuration: 6 × 10 GbE MAC, PCS, and FEC
Configuration
  • Dedicated SDM
  • Software-programmable device configuration
  • Serial flash interface
  • Configuration from parallel flash through external host
  • Fine-grained partial reconfiguration of core fabric—add or remove system logic while the device is operating
  • Dynamic reconfiguration of GTS transceivers and PLLs
  • Comprehensive set of security features including AES-256, SHA-256/384, and ECDSA-256/384 accelerators
  • PUF service
  • Platform attestation
  • Anti-tamper features
  • Configuration via protocol (CvP) using PCIe* 1.0, 2.0, 3.0, or 4.0
Functional safety
  • Functional Safety Data Package (FSDP)
  • Improved FPGA diagnostic measures enable use of Agilex™ 5 FPGAs in safety-critical applications
Software and tools
  • Quartus® Prime Pro Edition design suite with new compiler and Hyper-Aware design flow
  • New compile innovations in each Intel® oneAPI release
  • Transceiver toolkit
  • Platform Designer IP integration tool
  • Intel® DSP Builder for Intel® FPGAs advanced blockset
  • Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA)
4 0.65 mm is the minimum ball pitch and is not meant for signal trace routing. The VPBGA design meets the 0.8 mm design rules and the use of standard plated through hole (PTH) via.
5 Up to 3.5 Gbps for standard reference channel, and up to 2.5 Gbps for long reference channel.
6 Up to 2.5 Gbps for standard reference and long reference channels.
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