Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

11. Hard Processor System in Agilex™ 5 SoCs

The Agilex™ 5 SoCs hard processor system (HPS) consists of multicore Arm* processors, including a dual-core Arm* Cortex* -A76 and a dual-core Arm* Cortex* -A55 processors. Additionally, the HPS adds a system memory management unit that enables system-wide hardware virtualization.

With the HPS architecture improvements, the Agilex™ 5 SoCs fulfill the requirements of current and future embedded markets, including:

  • Wireless and wireline communications
  • Datacenter acceleration
  • Various industrial applications
Figure 9.  Agilex™ 5 SoCs HPS Block Diagram

Table 19.  Summary of Agilex™ 5 SoCs Key Features
Feature Description
Processor units
  • Multicore of dual-core Arm* Cortex* -A76 MPCore and dual-core Arm* Cortex* -A55 MPCore processor units
    • CPU frequency:
      • Dual-core Arm* Cortex* -A76—up to 1.8 GHz
      • Dual-core Arm* Cortex* -A55—up to 1.5 GHz
    • Arm* v8.2-A architecture
  • Run 64-bit and 32-bit Arm* instructions
  • 16-bit and 32-bit Thumb instructions for 30% reduction in memory footprint
  • Arm* Jazelle* runtime compilation target (RCT) execution architecture with 8-bit Java* bytecodes
  • Superscalar, variable-length, out-of-order pipeline with dynamic branch prediction
  • Improved Arm* Neon* media processing engine
  • Single-precision and double-precision floating-point unit
  • Arm* CoreSight* debug and trace technology
System memory management unit
  • Enables a unified memory model
  • Extends hardware virtualization into peripherals implemented in the FPGA fabric
Cache coherency unit Propagates changes in shared data stored in cache throughout the system to provide I/O coherency for co-processing elements
Cache memory Common Shared 2 MB L3 cache
Dual-core Arm* Cortex* -A76
  • 64 KB L1 I-cache and 64 KB L1 D-cache with ECC per core
  • 256 KB unified L2 data and instructions cache per core
Dual-core Arm* Cortex* -A55
  • 32 KB L1 I-cache and 32 KB L1 D-cache with ECC per core
  • 128 KB unified L2 data and instructions cache per core
On-chip memory 512 KB on-chip RAM
External SDRAM and flash memory Interfaces for HPS Hard memory controller
  • Supports DDR4, DDR5, LPDDR4, and LPDDR5
  • 40-bit (32-bit + 8-bit ECC)
  • ECC support including calculation, error correction, write-back correction, and error counters
  • Software-configurable priority scheduling on individual SDRAM bursts
  • Fully programmable timing parameter support for all JEDEC* -specified timing parameters
  • Multi-port front end (MPFE) interface to the hard memory controller, supporting AMBA* 4 AXI QoS for interface to the FPGA fabric
NAND flash controller
  • Integrated descriptor-based controller with DMA
  • Programmable hardware ECC support
  • Support for 8-bit and 16-bit flash devices
  • Compatible with the ONFI 1.x and 2.x specifications
  • Compatible with Toggle 1.x and 2.x specifications
SD/SDIO/eMMC controller
  • Integrated descriptor-based DMA controller
  • Supports CE-ATA digital commands
  • Supports SD devices up to version 6.1
  • Supports SDIO devices up to version 4.1
  • Supports SD/eMMC devices up to version 5.1
  • Supports SD SDR12, SDR25, SDR50, SDR104, and DDR50
  • Supports eMMC legacy, high-speed SDR, high-speed DDR, HS200, and HS400
  • Does not support UHS-II and UHS-III interfaces
DMA controller
  • Two controllers with four channels each
  • Supports up to 48 peripheral handshake interfaces
Communication interface controllers Ethernet MAC
  • Three Ethernet MACs supporting 10 Mbps, 100 Mbps, 1 Gbps, and 2.5 Gbps with integrated DMA and TSN support
  • Ethernet standards with TSN endpoint functionality compliant to:
    • IEEE 1588-2008 advanced timestamps: Precision Time Protocol (PTP), 2-steps, PTP offload and timestamping
    • IEEE 802.1AS: Timing and synchronization
    • IEEE 802.1Qav: Time-sensitive streams forwarding and queuing
    • IEEE 802.1Qbv: Time-scheduled traffic enhancements
    • IEEE 802.1Qbu: Frame pre-emption
    • IEEE 802.3br: Interspersing express traffic
  • Ethernet interfaces:
    • Supports RGMII operating mode at 10 Mbps, 100 Mbps, and 1 Gbps data rates through HPS I/O
    • Supports RGMII operating modes at 10 Mbps, 100 Mbps, and 1 Gbps data rates through FPGA HVIO with GMII–to–RGMII soft adapter in FPGA logic
    • Supports SGMII operating mode at 1 Gbps (1000BASE-X) or 10 Mbps, 100 Mbps, and 1 Gbps (SGMII) data rates with SGMII PCS soft IP through TDS I/O
    • Supports SGMII+ operating mode at 10 Mbps, 100 Mbps, 1 Gbps, and 2.5 Gbps data rates with SGMII+ PCS soft IP and serial transceiver interface through FPGA I/O
  • One USB OTG controller
  • Dual-role device (device and host functions)
    • High-speed (480 Mbps)
    • Full-speed (12 Mbps)
    • Low-speed (1.5 Mbps)
    • Supports USB 1.1 (full-speed and low-speed)
  • Integrated descriptor-based scatter-gather DMA
  • Support for external ULPI PHY
  • Up to 16 bidirectional endpoints, including control endpoint
  • Up to 16 host channels
  • Supports generic root hub
  • Configurable to USB OTG 1.3 and USB OTG 2.0 modes
USB 3.1 Gen1
  • Supports both device and host controller modes
    • Both USB 3.1 and USB 2.0 interfaces must be configured as device or host; mixing modes is not supported
  • Supports up to 5 Gbps if configured for USB 3.1 Gen1 and interfaced with the transceiver
  • Supports up to 480 Mbps if configured for USB 2.0 and interfaced with the HPS I/O
  • Five I2C controllers, three can be used by the Ethernet MAC for MIO to external PHY
  • Support 100 Kbps and 400 Kbps modes
  • Support 7-bit and 10-bit addressing modes
  • Support master and slave operating modes
  • Two I3C controllers
    • One configured as the primary master
    • One configured as the secondary master
  • Supports FM, FM+, and SDR data rates up to 12.5 Mbps
  • Two UART 16550-compatible controllers
  • Programmable baud rate up to 115.2 kilobaud
  • Four SPI (two masters, two slaves)
  • Supports full duplex and half duplex
  • Four general-purpose timers
  • Five watchdog timers
  • 48 HPS direct I/Os allow HPS peripherals to connect directly to the I/Os
  • Up to two FPGA fabric I/O banks assignable to the HPS for HPS DDR access
Interconnect to logic core HPS–to–FPGA bridge
  • Allows HPS bus masters to access bus slaves in FPGA fabric
  • Configurable 32-, 64-, or 128-bit AMBA* AXI data interface allows high-bandwidth HPS master transactions to FPGA fabric
  • Supports up to 256 gigabytes (GB) of address space
Lightweight HPS–to–FPGA bridge
  • Lightweight 32-bit AMBA* AXI interface suitable for low bandwidth register access from HPS to soft peripherals in the FPGA fabric
  • Supports up to 512 MB of address space
FPGA–to–HPS bridge
  • 256 bits FPGA–to–HPS interface targeting the HPS peripherals and shared SDRAM
  • Shared SDRAM accessible using non-coherent18 or hardware-supported I/O coherent transactions
FPGA–to–SDRAM bridge
  • 64, 128, or 256 bits FPGA–to–SDRAM interface targeting the DDR I/O
  • Supports only non-coherent18 transactions
18 For non-coherent transactions, ensure that the HPS and FPGA soft logic do not interfere in the SDRAM space of each other.