Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs

The Agilex™ 5 FPGAs and SoCs tier consists of the performance-optimized D-Series FPGAs and the power-optimized E-Series FPGAs.
Table 1.   Agilex™ 5 FPGAs and SoCs Series
Feature and Innovation D-Series FPGA E-Series FPGA
Device Group A Device Group B
Process technology Intel® 7
Architecture Monolithic die
Packaging Variable Pitch BGA (VPBGA) package with minimum ball pitch of 0.65 mm 1 for smaller form factor and to help reduce the number of PCB layers VPBGA package with minimum ball pitch of 0.65 mm 1 for smaller form factor and to help reduce the number of PCB layers
  • VPBGA package with minimum ball pitch of 0.65 mm 1 for smaller form factor and to help reduce the number of PCB layers
  • Rectangular package and standard pattern ball array with smaller ball pitch of 0.5 mm for smaller form factor
Core fabric Second generation Hyperflex® core fabric
Logic elements 103 thousand to 644 thousand 138 thousand to 656 thousand 50 thousand to 656 thousand
On-chip RAM MLAB and M20K
69 Mb 38 Mb 38 Mb
Variable precision DSP Industry-leading digital signal processing (DSP) support with up to 38 TFLOPS
AI Tensor block Yes
Clocking and PLL
  • Programmable clock tree synthesis for flexible, low power, and low skew clocking
  • I/O PLL supports integer mode with precise frequency synthesis for general purpose I/O, external memory interfaces, LVDS, and fabric usage
  • Transmit PLL (TX PLL) supports fractional synthesis and ultra-low jitter with LC tank-based PLL for transceiver usage.
General Purpose I/Os
  • 1.0 V to 1.3 V high-speed I/O (HSIO)
  • 1.8 V to 3.3 V high-voltage I/O (HVIO)
MIPI* D-PHY* v2.5 Up to 3.5 Gbps 2 per lane Up to 3.5 Gbps 2 per lane Up to 2.5 Gbps 3 per lane
External memory interface Fourth generation scalable integrated hard memory controllers and PHY
  • 3,200 Mbps DDR4
  • 4,000 Mbps DDR5
  • 4,267 Mbps LPDDR4
  • 4,267 Mbps LPDDR5
  • 2,667 Mbps DDR4
  • 3,600 Mbps DDR5
  • 3,733 Mbps LPDDR4
  • 3,733 Mbps LPDDR5
  • 2,400 Mbps DDR4
  • 2,667 Mbps LPDDR4
  • 2,400 Mbps LPDDR5
Cryptography SDM supports Advanced Encryption Standard (AES)
Transceiver hard IPs
  • Multiple Gigabit Ethernet (GbE) network interface connectivity in one device
  • PCS and PCIe* hard IPs free up valuable core logic resources, save power, and increase your productivity
  • Hardened 10 and 25 GbE media access control (MAC), physical coding sublayer (PCS), and forward error correction (FEC) with IEEE 1588 support
  • Up to 28.1 Gbps non-return-to-zero (NRZ)
  • Up to PCIe* 4.0 ×8
  • Hardened 10 and 25 GbE MAC, PCS, and FEC with IEEE 1588 support
  • Up to 28.1 Gbps NRZ
  • PCIe* 4.0 ×4
  • Hardened 10 GbE MAC, PCS, and FEC with IEEE 1588 support
  • Up to 17.16 Gbps NRZ
  • Up to PCIe* 4.0 ×4
SDM

Dedicated secure device manager (SDM) that:

  • Manages FPGA configuration process and all security features
  • Performs authenticated FPGA configuration and HPS boot
  • Supports FPGA bitstream encryption, secure key provisioning, and physically unclonable function (PUF) key storage
  • Manages runtime sensors and supports active tamper detection and responses
  • Supports platform attestation using the security protocol and data model (SPDM) protocol
  • Provides access to hardened cryptographic engines as a service
HPS

(SoCs only)

Hard processor system (HPS) with embedded multicore Arm* processors:

  • Dual-core 64-bit Arm* Cortex* -A76 up to 1.8 GHz
  • Dual-core 64-bit Arm* Cortex* -A55 up to 1.5 GHz
Power saving Comprehensive set of advanced power saving features that deliver up to 40% lower power compared to previous generation high-performance FPGAs
1 0.65 mm is the minimum ball pitch and is not meant for signal trace routing. The VPBGA design meets the 0.8 mm design rules and the use of standard plated through hole (PTH) via.
2 Up to 3.5 Gbps for standard reference channel, and up to 2.5 Gbps for long reference channel.
3 Up to 2.5 Gbps for standard reference and long reference channels.
Level Two Title