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1. Overview of the Intel Agilex® 5 FPGAs and SoCs
2. Intel Agilex® 5 FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex® Core Architecture
4. Adaptive Logic Module in Intel Agilex® 5 FPGAs and SoCs
5. Internal Embedded Memory in Intel Agilex® 5 FPGAs and SoCs
6. Variable-Precision DSP in Intel Agilex® 5 FPGAs and SoCs
7. Core Clock Network in Intel Agilex® 5 FPGAs and SoCs
8. General Purpose I/Os in Intel Agilex® 5 FPGAs and SoCs
9. I/O PLLs in Intel Agilex® 5 FPGAs and SoCs
10. External Memory Interface in Intel Agilex® 5 FPGAs and SoCs
11. Hard Processor System in Intel Agilex® 5 SoCs
12. Transceivers in Intel Agilex® 5 FPGAs and SoCs
13. MIPI* Protocols Support in Intel Agilex® 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Intel Agilex® 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Intel Agilex® 5 FPGAs and SoCs
16. Device Configuration and the SDM in Intel Agilex® 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Intel Agilex® 5 FPGAs and SoCs
18. Device Security for Intel Agilex® 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Intel Agilex® 5 FPGAs and SoCs
20. Power Management for Intel Agilex® 5 FPGAs and SoCs
21. Intel® Software and Tools for Intel Agilex® 5 FPGAs and SoCs
22. Revision History for the Intel Agilex® 5 FPGAs and SoCs Device Overview
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13. MIPI* Protocols Support in Intel Agilex® 5 FPGAs and SoCs
The Intel Agilex® 5 FPGAs and SoCs support native MIPI* IP D-PHY* . The devices support MIPI* D-PHY* v2.5 at up to 3.5 Gbps20 per lane. The Intel Agilex® 5 FPGAs support MIPI* D-PHY* high-speed and low-power signaling modes without requiring external components.
Features of the MIPI* IP D-PHY* :
- Enables unidirectional multi-lane configurations—1, 2, 4, or 8 lanes
- Supports low-power and high-speed signaling up to 3.5 Gbps 20 per lane
The MIPI* IP D-PHY* implements MIPI* transmit and receive interfaces for Intel Agilex® 5 FPGAs in accordance to the following protocols:
- Camera Serial Interface (CSI-2) version 3.0 with underlying D-PHY* standard
- Display Serial Interface (DSI-2) version 2.0 with underlying D-PHY* standard
Protocol | D-Series FPGA | E-Series FPGA | |
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Device Group A | Device Group B | ||
CSI-2 |
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DSI-2 |
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Figure 12. MIPI* Receiver Block Diagram
Figure 13. MIPI* Transmitter Block Diagram
20 Up to 3.5 Gbps for standard reference channel, and up to 2.5 Gbps for long reference channel.
21 Up to 2.5 Gbps for standard reference and long reference channels.