Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 1/12/2024
Public
Document Table of Contents

13. MIPI* Protocols Support in Intel Agilex® 5 FPGAs and SoCs

The Intel Agilex® 5 FPGAs and SoCs support native MIPI* IP D-PHY* . The devices support MIPI* D-PHY* v2.5 at up to 3.5 Gbps20 per lane. The Intel Agilex® 5 FPGAs support MIPI* D-PHY* high-speed and low-power signaling modes without requiring external components.

Features of the MIPI* IP D-PHY* :

  • Enables unidirectional multi-lane configurations—1, 2, 4, or 8 lanes
  • Supports low-power and high-speed signaling up to 3.5 Gbps 20 per lane

The MIPI* IP D-PHY* implements MIPI* transmit and receive interfaces for Intel Agilex® 5 FPGAs in accordance to the following protocols:

  • Camera Serial Interface (CSI-2) version 3.0 with underlying D-PHY* standard
  • Display Serial Interface (DSI-2) version 2.0 with underlying D-PHY* standard
Table 23.   MIPI* CSI-2 and DSI-2 Performance in Intel Agilex® 5 FPGAs and SoCs
Protocol D-Series FPGA E-Series FPGA
Device Group A Device Group B
CSI-2
  • CSI-2 version 3, up to eight lanes
  • D-PHY* v2.5 at up to 3.5 Gbps 20
  • CSI-2 version 3, up to eight lanes
  • D-PHY* v2.5 at up to 3.5 Gbps 20
  • CSI-2 version 3, up to eight lanes
  • D-PHY* v2.5 at up to 2.5 Gbps21
DSI-2
  • DSI-2 version 2, up to four lanes
  • D-PHY* v2.5 at up to 3.5 Gbps
  • DSI-2 version 2, up to four lanes
  • D-PHY* v2.5 at up to 3.5 Gbps 20
  • DSI-2 version 2, up to four lanes
  • D-PHY* v2.5 at up to 2.5 Gbps21
Figure 12.  MIPI* Receiver Block Diagram


Figure 13.  MIPI* Transmitter Block Diagram


20 Up to 3.5 Gbps for standard reference channel, and up to 2.5 Gbps for long reference channel.
21 Up to 2.5 Gbps for standard reference and long reference channels.