Visible to Intel only — GUID: xhv1652276200276
Ixiasoft
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
Visible to Intel only — GUID: xhv1652276200276
Ixiasoft
2.3. Agilex™ 5 FPGAs and SoCs Package Options
In the following figures:
- The arrows indicate the package migration paths. The shades represent the devices included in each path.
- To achieve full I/O migration across devices in the same migration path, restrict I/Os and transceivers utilization to match the device with the lowest I/O and transceiver counts.
Figure 2. Package Options, Migrations, and I/O Pins—D-Series
Figure 3. Package Options, Migrations, and I/O Pins—E-Series
Note: For the VPBGA packages, 0.65 mm is the minimum ball pitch and is not meant for signal trace routing. The VPBGA design meets the 0.8 mm design rules and the use of standard plated through hole (PTH) via.
Related Information