Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

2.3. Agilex™ 5 FPGAs and SoCs Package Options

In the following figures:

  • The arrows indicate the package migration paths. The shades represent the devices included in each path.
  • To achieve full I/O migration across devices in the same migration path, restrict I/Os and transceivers utilization to match the device with the lowest I/O and transceiver counts.
Figure 2. Package Options, Migrations, and I/O Pins—D-Series

Figure 3. Package Options, Migrations, and I/O Pins—E-Series

Note: For the VPBGA packages, 0.65 mm is the minimum ball pitch and is not meant for signal trace routing. The VPBGA design meets the 0.8 mm design rules and the use of standard plated through hole (PTH) via.