Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

9. I/O PLLs in Agilex™ 5 FPGAs and SoCs

The I/O banks of the Agilex™ 5 FPGAs and SoCs contain I/O PLLs for use in I/O interfacing or fabric clocking.
Table 15.  I/O PLLs in Different I/O Bank Types
I/O Bank Type Bank I/O PLL Fabric-Feeding I/O PLL
HSIO (96 I/Os) 2 1
HVIO (2×20 I/Os) 1

You can use the I/O PLLs for general purpose applications in the core fabric, such as clock network delay compensation and zero-delay clock buffering.

The I/O PLLs are situated adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O bank. This placement creates a tight coupling of the PLLs with the I/Os that need them. The architecture simplifies designing external memory and high-speed LVDS interfaces, and eases timing closure.