Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

1.4. Additional Features for Agilex™ 5 SoCs

In addition to the common features of the Agilex™ 5 FPGAs and SoCs, the Agilex™ 5 SoCs provide additional features.
Table 3.  Features Specific to Agilex™ 5 SoCs
SoC Subsystem Feature Description
HPS Multiprocessor unit core
  • Multicore Arm* processors, including dual-core Arm* Cortex* -A76 MPCore and dual-core Arm* Cortex* -A55 MPCore processors, with Arm* CoreSight* debug and trace technology
  • Scalar floating-point unit supporting single and double precision
  • Arm* Neon* technology media processing engine for each processor
System controllers
  • System memory management unit (SMMU)
  • Cache coherency unit (CCU)
Cache
  • Arm* Cortex* -A76:
    • Level 1 cache per core:
      • 64 kilobytes (KB) L1 instruction cache with parity
      • 64 KB L1 data cache with ECC
    • Level 2 cache per core: Unified 256 KB L2 data and instructions cache with ECC
  • Arm* Cortex* -A55:
    • Level 1 cache per core:
      • 32 KB L1 instruction cache with parity
      • 32 KB L1 data cache with ECC
    • Level 2 cache per core: Unified 128 KB L2 data and instructions cache with ECC
  • Shared level 3 cache: 2 megabytes (MB) L3 cache
On-chip memory 512 KB on-chip RAM
Direct memory access (DMA) Eight-channel DMA controller
Ethernet MAC (TSN)
  • Three 10 Mbps/100 Mbps/1 Gbps/2.5 Gbps Ethernet MACs with integrated DMA and Time-Sensitive Networking (TSN) support
  • 1 Gbps and 2.5 Gbps (2.5 Gbps requires soft paths to the transceivers)
USB
  • One USB 2.0 On-The-Go (OTG) with integrated DMA
  • One USB 3.1 Gen 1
UART Two UART 16550-compatible controllers
Serial peripheral interface (SPI) controller Four SPI (two masters and two slaves)
I2C Five I2C controllers
I3C Two I3C controllers
SD/SDIO/eMMC controller
  • SD/eMMC devices up to version 5.1
  • SD devices up to version 6.1
  • SDIO devices up to version 4.1
NAND flash controller
  • One ONFI 1.x and 2.x
  • 8 bit and 16 bit support
  • Compatible with Toggle 1.x and 2.x specifications
GPIO Maximum of 48 software-programmable GPIOs
Timers
  • Four general-purpose timers
  • Five watchdog timers
SDM
  • Secure boot
  • AES encryption
  • Secure Hash Algorithms (SHA) and Elliptic Curve Digital Signature Algorithm (ECDSA) authentications
External memory interface

Hard memory controllers:

  • D-Series—DDR4, DDR5, LPDDR4, and LPDDR5
  • E-Series:
    • Device Group A—DDR4, DDR5, LPDDR4, and LPDDR5
    • Device Group B—DDR4, LPDDR4, and LPDDR5
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