Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

Document Version Changes
  • Added the adaptive logic module (ALM) counts.
  • Removed package M16A from the A5E 028B device.
  • Retitled the "Available Options" topic to "Part Number Decoder".
  • Added 1.0 V LVCMOS support for the HSIO.
  • Added notes that the minimum ball pitch of 0.65 nm is not meant for signal trace routing.
  • Updated the fabric-feeding I/O PLL count for the following devices:
    • A5D 051 and A5D 064—from 13 to 15
    • A5E 043A and A5E 043B—from 11 to 13
  • Added a figure that shows the available ordering part numbers.
  • Removed support for ACE5-Lite cache stashing for the FPGA–to–HPS bridge.
  • Updated references to "Balls Anywhere" to "Variable Pitch BGA (VPBGA)".
  • Updated the package options and vertical migrations for E-Series FPGAs to remove information about conditional migration path.
  • Updated the package options and vertical migrations:
    • Added package B18A.
    • Updated pin counts for packages B23B, B23A, and B32A.
    • Added devices to package B23A of the E-Series FPGA Device Group A.
  • Updated the supported DDR4 maximum width for E-Series FPGAs
  • Updated E-Series FPGA Device Group B to support up to PCIe 4.0.
  • Assigned "GTS" naming to the transceivers.
  • Updated information about the HPS L2 cache.
  • Updated the E-Series HPS processors speeds:
    • Dual core ARM® Cortex®-A76—from up to 1.6 GHz to up to:
      • Device Group A—1.8 GHz
      • Device Group B— 1.4 GHz
    • Dual core ARM® Cortex®-A55—from up to 1.33 GHz to up to:
      • Device Group A—1.5 GHz
      • Device Group B— 1.25 GHz
  • Updated the HPS block diagram.
  • Removed ONFI 3.x and 4.x from HPS NAND flash controller.
  • Updated HPS Ethernet MAC information:
    • Updated the TSN endpoint functionality compliance.
    • Removed MII, RMII, and GMII support.
    • Updated RGMII support.
2023.01.10 Initial release.