Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs

Agilex™ 5 devices feature a robust SEU error detection and correction circuitry that protects the configuration RAM (CRAM) programming bits and M20K user memories.

To protect the CRAM, a parity checker circuit with integrated ECC runs continuously to automatically correct single-bit or double-bit errors and detect higher order multi-bit errors. The optimized physical layout of the CRAM array makes most multi-bit upsets appear as independent single-bit or double-bit errors. Therefore, the CRAM ECC circuitry can automatically correct these errors.

The user memories also has integrated ECC circuitry and are also layout-optimized for error detection and correction.

To provide a complete SEU mitigation solution, a soft IP and the Quartus® Prime software support the SEU error detection and correction hardware. The following components make up the complete solution:

  • Hard error detection and correction for CRAM and M20K user memory blocks
  • Optimized memory cells physical layout to minimize the probability of an SEU
  • Sensitivity processing soft IP that reports if a CRAM upset affects a used or unused bit
  • Fault injection soft IP with Quartus® Prime software support to change CRAM bits state for testing
  • Hierarchy tagging feature in the Quartus® Prime software
  • Triple modular redundancy (TMR) for the SDM and critical on-chip state machines

Agilex™ 5 FPGAs and SoCs also support the following SEU mitigation features:

  • Fast SEU detection notification through an IP that connects the LSM pin to the fabric. This notification allows the fabric soft logic to detect reported SEU events faster. You can then retrieve further SEU details through the SDM mailbox.
  • External scrubbing for SEU errors that are not automatically correctable. You can create scrubbing bitstream—up to one sector granularity—to scrub the SEU-corrupted configuration bits while keeping the remaining parts of the device intact.
  • Single-bit ECC injection, ECC error detection, and reporting on memory in the configuration system. You can test the ECC detection logic by issuing ECC injection commands and querying the ECC status from the SDM.

Furthermore, Agilex™ 5 FPGAs and SoCs are built on the FinFET-based Intel® 7 technology. FinFET transistors are less susceptible to SEUs compared to conventional planar transistors.