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1. Overview of the Intel Agilex® 5 FPGAs and SoCs
2. Intel Agilex® 5 FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex® Core Architecture
4. Adaptive Logic Module in Intel Agilex® 5 FPGAs and SoCs
5. Internal Embedded Memory in Intel Agilex® 5 FPGAs and SoCs
6. Variable-Precision DSP in Intel Agilex® 5 FPGAs and SoCs
7. Core Clock Network in Intel Agilex® 5 FPGAs and SoCs
8. General Purpose I/Os in Intel Agilex® 5 FPGAs and SoCs
9. I/O PLLs in Intel Agilex® 5 FPGAs and SoCs
10. External Memory Interface in Intel Agilex® 5 FPGAs and SoCs
11. Hard Processor System in Intel Agilex® 5 SoCs
12. Transceivers in Intel Agilex® 5 FPGAs and SoCs
13. MIPI* Protocols Support in Intel Agilex® 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Intel Agilex® 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Intel Agilex® 5 FPGAs and SoCs
16. Device Configuration and the SDM in Intel Agilex® 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Intel Agilex® 5 FPGAs and SoCs
18. Device Security for Intel Agilex® 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Intel Agilex® 5 FPGAs and SoCs
20. Power Management for Intel Agilex® 5 FPGAs and SoCs
21. Intel® Software and Tools for Intel Agilex® 5 FPGAs and SoCs
22. Revision History for the Intel Agilex® 5 FPGAs and SoCs Device Overview
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5. Internal Embedded Memory in Intel Agilex® 5 FPGAs and SoCs
The embedded memory blocks in Intel Agilex® 5 FPGAs and SoCs are similar to the embedded memory of previous generation Intel® FPGAs.
Feature | MLAB | M20K |
---|---|---|
Usage | For wide and shallow memory configurations | For supporting larger memory configurations |
Block size | 640 bits | 20 kilobits |
Configurations |
|
|
Hard ECC | — | Yes |
Modes | Single-port RAM, dual-port RAM, FIFO, ROM, and shift register |