| Protocol |
- LPDDR5—two dynamic frequency scaling (DFS) frequencies
- DDR4 and DDR5—up to two chip selects and up to two 3D stacks
|
| Interface |
- Fully pipelined command, read, and write data interfaces to the controller
- Arm* AMBA* 4 AXI compliance including AXI ordering rules:
- Four priority quality of service (QoS) levels
- Programmable address mapping
- Exclusive monitors
|
| Scheduling |
- Software-configurable priority scheduling on individual SDRAM bursts
- Advanced bank look-ahead features for high memory throughput
- Configurable for one of these placement orders:
- Out-of-order placement for writes
- In-order placement for writes from the same port
- In-order placement for writes from the same AXI master
- Configurable for in-order scheduling for reads and writes
- Support read or write grouping
|
| Timing |
Fully programmable timing parameter support for all JEDEC* -specified timing parameters |
| Refresh |
- All bank refresh or per bank refresh (if supported by memory)
- Refresh management for DDR5
|
| ECC |
- Error correction code (ECC) support including calculation, error correction, write-back correction, and error counters
- Hardened ECC support including configurations for various ECC types with programmable single-bit and double-bit error reporting and automatic correction:
- In-line ECC, out-of-band ECC, link ECC, end-to-end (user) ECC, or no ECC
- Supports standard single bit error correction and double bit error detection
- Support for ECC passthrough for fabric ECC with 8 bits of ECC per 64 bits of data
- Supports scrubbing
|
| Power states |
Low power DRAM states including active power down, precharge power down, and self-refresh power down states for DRAM:
- Under register control; or
- Based on idle times
|
| Training |
Initial and periodic ZQ calibration (LPDDR4, LPDDR5, DDR5) |
| Verification |
- Performance monitoring statistics
- Memory test for DDR memories through register control
|