Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

2.2. Agilex™ 5 FPGAs and SoCs E-Series

Table 7.  E-Series FPGA Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device Group Type Device

Logic Element

Adaptive Logic Module M20K

MLAB

 DSP
Count

Size (Mb)

 Count

Size (Mb)

 18×19 Multipliers

Peak INT8

(TOPS9 )

Device Group A A5E 013A 138,060 46,800 358 6.99 2,340 1.43 376 5.78
A5E 028A 282,256 95,680 716 13.98 4.784 2.92 752 11.55
A5E 043A 434,240 147,200 1,050 20.51 6,720 4.10 1,128 17.33
A5E 052A 523,920 177,600 1,288 25.16 8,440 5.15 1,352 20.78
A5E 065A 656,080 222,400 1,611 31.46 11,120 6.79 1,692 25.99
Device Group B A5E 005B 50,445 17,100 130 2.54 850 0.52 130 1.70
A5E 007B 69,030 23,400 179 3.50 1,170 0.71 188 2.46
A5E 008B 85,196 28,880 229 4.47 1,780 1.09 232 3.05
A5E 013B 138,060 46,800 358 6.99 2,340 1.43 376 4.93
A5E 028B 282,256 95,680 716 13.98 4,784 2.92 752 9.85
A5E 043B 434,240 147,200 1,050 20.51 6,720 4.10 1,128 14.78
A5E 052B 523,920 177,600 1,288 25.16 8,440 5.15 1,352 17.72
A5E 065B 656,080 222,400 1,611 31.46 11,120 6.79 1,692 22.17
Table 8.  E-Series FPGA Family Plan—I/Os and InterfacesThe values in this table are maximum resources or performance.
Device Group Type Device

HVIO

(1.8 V–3.3 V)

HSIO

(1.0 V–1.3 V)

PLL Count

1.3 V LVDS Pairs

at 1.6 Gbps

DDR4,

DDR510, LPDDR4, LPDDR5 Interface

(×32)

 MIPI*

D-PHY*

Interface
I/O PLL Fabric-Feeding I/O PLL11
Device Group A A5E 013A 200 192 4 8 96 2 14
A5E 028A 200 192 4 10 96 2 14
A5E 043A 120 384 8 13 192 4 28
A5E 065A 120 384 8 13 192 4 28
A5E 052A 120 384 8 13 192 4 28
Device Group B A5E 005B 160 96 2 5 48 1 7
A5E 007B 160 96 2 5 48 1 7
A5E 008B 200 192 4 8 96 2 14
A5E 013B 200 192 4 8 96 2 14
A5E 028B 200 192 4 10 96 2 14
A5E 043B 120 384 8 13 192 4 28
A5E 052B 120 384 8 13 192 4 28
A5E 065B 120 384 8 13 192 4 28
Table 9.  E-Series FPGA Family Plan—Transceivers and HPS

The values in this table are maximum resources or performance.

Device Group Type Device

Transceiver

12

PCIe* 4.0 ×4

Gigabit Ethernet13

(MAC & PCS)

HPS
Processor Cache Size
Device Group A A5E 013A 4 1 1
  • Dual core Arm* Cortex* -A76 up to 1.8 GHz
  • Dual core Arm* Cortex* -A55 up to 1.5 GHz
  • Shared: 2 MB L3
  • Cortex* -A76:
    • 64 KB L1
    • 256 KB L2
  • Cortex* -A55:
    • 32 KB L1
    • 128 KB L2
A5E 028A 12 3 3
A5E 052A 24 6 4
A5E 065A 24 6 6
A5E 043A 16 4 4
Device Group B A5E 005B — — — — —
A5E 007B — — — — —
A5E 008B 4 1 1
  • Dual core Arm* Cortex* -A76 up to 1.4 GHz
  • Dual core Arm* Cortex* -A55 up to 1.25 GHz
  • Shared: 2 MB L3
  • Cortex* -A76:
    • 64 KB L1
    • 256 KB L2
  • Cortex* -A55:
    • 32 KB L1
    • 128 KB L2
A5E 013B 4 1 1
A5E 028B 12 3 3
A5E 043B 16 4 4
A5E 052B 24 6 6
A5E 065B 24 6 6
9 Tera Operations Per Second
10 Applicable only to E-Series Device Group A FPGAs.
11 The fabric-feeding I/O PLL counts include the System PLL in the GTS transceiver banks. You can use the System PLL for core fabric usage if you do not use it for the transceiver.
12 E-Series Device Group A FPGAs: 28.1 Gbps maximum rate. E-Series Device Group B FPGAs: 17.16 Gbps maximum rate.
13 E-Series Device Group A FPGAs: 10/25 GbE. E-Series Device Group B FPGAs: 10 GbE.
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