Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

3. Second Generation Hyperflex® Core Architecture

The Agilex™ 5 FPGAs and SoCs are based on a core fabric featuring the second generation Hyperflex® core architecture.
Table 10.  Advantages of the Hyperflex® Core ArchitectureThis table lists some of the advantages of the Hyperflex® core architecture.
Advantage Description
Higher throughput

Delivers, on average, 50% higher core clock frequency performance in designs from previous generation high-end FPGAs to obtain throughput breakthroughs.

Improved power efficiency Uses reduced IP size to consolidate designs that previously spanned multiple devices into a single device. This consolidation reduces power requirement by up to 42% compared to Stratix® 10 FPGAs.
Greater design functionality Uses faster clock frequency to reduce bus widths and reduce IP size. The reduced bus widths and IP size free up additional FPGA resources to add greater functionality.
Increased designer productivity Boosts performance with less routing congestion and fewer design iterations using the Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure.

Additional to traditional ALM user registers, the Hyperflex® core architecture adds bypassable registers called Hyper-Registers:

  • Distributed throughout the FPGA fabric.
  • Available on every interconnect routing segment and at the inputs of all functional blocks.
Figure 5. Bypassable Hyper-Register

In the second generation Hyperflex® core architecture, Intel optimized the number of registers to improve timing closure time and fabric area utilization.

Figure 6.  Hyperflex® Core Architecture

The Hyper-Registers enable you to achieve core performance increases using key design techniques. If you implement these design techniques, the Hyper-Aware design tools automatically utilizes the Hyper-Registers to achieve maximum core clock frequency:

  • Fine grain Hyper-Retiming to eliminate critical paths
  • Zero-latency Hyper-Pipelining to eliminate routing delays
  • Flexible Hyper-Optimization for best-in-class performance