Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

20. Power Management for Agilex™ 5 FPGAs and SoCs

The Agilex™ 5 FPGA product family offers standard power devices that support SmartVID and fixed core voltage devices with limited core speed options.

The Agilex™ 5 FPGAs and SoCs achieve significant total power reduction:

  • D-Series—up to 42% compared to Stratix® 10 FPGAs
  • E-Series—up to 50% compared to Cyclone® V FPGAs

To achieve the total power reduction, the Agilex™ 5 FPGAs and SoCs capitalizes on:

  • Advanced Intel® 7 technology
  • Second generation Hyperflex® core architecture
  • SmartVID or fixed core voltage
  • Other power reduction techniques such as power island and power gating
Table 26.   Agilex™ 5 FPGAs and SoCs Power Options
Device Type Series Description
  • D-Series
  • E-Series Device Group A
  • The devices operate at the optimum core voltage that meets the VID power limit and required device performance for various FPGA applications.
  • A factory-programmed code allows a PMBus voltage regulator to operate at the optimum core voltage to meet the device VID power limit and performance specifications. Therefore, you must mandatorily drive the VCC and VCCP core voltage supplies of the SmartVID device with a dedicated PMBus voltage regulator.
Fixed voltage E-Series Device Group B
  • The devices support 0.75 V, 0.78 V, and 0.8 V.
  • Using a fixed low core voltage,the devices further reduce the total power consumption.
  • These fixed voltage devices have lower static power than the SmartVID standard power devices while maintaining device performance.

The power island and power gating feature powers down unused resources in Agilex™ 5 devices to reduce static power consumption. During configuration, the Quartus® Prime software automatically powers down specific unused resources such as the DSP or M20K blocks.

Furthermore, Agilex™ 5 devices feature industry-leading low power transceivers and include a number of hard IP blocks. The hard IP blocks not only reduce logic resources utilization but also deliver substantial power savings compared to soft implementations. The hard IP blocks generally consume up to 50% less power than equivalent soft logic implementations.