Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs

All Agilex™ 5 FPGAs and SoCs contain an SDM. The SDM is a triple-redundant processor that serves as the point of entry into the device for all JTAG and configuration commands. Additionally, the SDM in the Agilex™ 5 FPGAs and SoCs enables system certification to FIPS140-3 layer 2 compliance.

The SDM bootstraps the HPS in Agilex™ 5 SoCs. This bootstrapping ensures that the HPS boots using the same security features available to the FPGA.

Figure 16. SDM Block Diagram

During configuration, the Agilex™ 5 FPGA or SoC divides into logical sectors. A local sector manager (LSM) manages each logical sector. The SDM passes configuration data to each LSMs across the on-chip configuration network.

Advantages of the sector-based approach:

  • Enables independent configuration of the sectors—one at a time or in parallel
  • Achieves simplified sector configuration and reconfiguration
  • Reduces overall configuration time caused by inherent parallelism.

The Agilex™ 5 FPGAs and SoCs use the same sector-based approach to respond to SEUs and security attacks.

Although the sectors provide a logical separation for device configuration and reconfiguration, the sectors overlay the normal rows and columns of FPGA logic and routing:

  • No impact to the Quartus® Prime software place and route
  • No impact to the timing of logic signals that cross the sector boundaries

The SDM enables robust, secure, and fully-authenticated device configuration. Additionally, the SDM allows you to customize the configuration scheme, enhancing device security.

Advantages of the SDM-based device configuration approach:

  • Provides a dedicated secure configuration manager
  • Reduces device configuration time because sectors are configured in parallel
  • Enables an updatable configuration process
  • Supports partial reconfiguration
  • Allows remote system update
  • Supports zeroization of whole device or individual sectors
Table 24.  Supported Configuration Schemes for Agilex™ 5 FPGAs
Configuration Scheme Data Width Maximum Data Rate
Active Serial (AS) normal and fast modes 4 bits 4 bits × 166 MHz = 664 Mbps
Avalon® streaming interface ×16 23 16 bits 16 bits × 125 MHz = 2 Gbps
Avalon® streaming interface ×8 8 bits 8 bits × 125 MHz = 1 Gbps
JTAG 1 bit 1 bit × 30 MHz = 30 Mbps
Configuration via Protocol (CvP) ×1, ×2, ×4 and ×8 lanes

The maximum data rate depends on the PCIe* generation and number of lanes. Typically, the data rate of the internal configuration data path of the device, instead of the width of the PCIe* link, limits the configuration data width.

23 Not supported in E-Series A5E 005B and A5E 007B devices.