Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

2.1. Agilex™ 5 FPGAs and SoCs D-Series

Table 4.  D-Series FPGA Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device

Logic Element

 Adaptive Logic Module M20K MLAB DSP
Count

Size (Mb)

 Count

Size (Mb)

 18×19 Multiplier

Peak INT8

(TOPS 7 )

A5D 010 103,250 35,000 534 10.43 1,780 1.09 552 8.48
A5D 025 254,054 86,120 1,281 25.02 3,420 2.09 1,472 22.61
A5D 031 318,600 108,000 1,602 31.29 5,400 3.30 1,840 28.26
A5D 051 515,070 174,600 2.563 50.06 8,440 5.15 2,944 45.22
A5D 064 644,280 218,400 3,204 62.58 10,920 6.67 3,680 56.22
Table 5.  D-Series FPGA Family Plan—I/Os and InterfacesThe values in this table are maximum resources or performance.
Device

HVIO

(1.8 V–3.3 V)

HSIO

(1.0 V–1.3 V)

PLL Count

1.3 V LVDS Pairs

at 1.6 Gbps

External Memory Interface

MIPI*

D-PHY* Interface

I/O PLL Fabric-Feeding I/O PLL8

DDR4

(×64)

DDR4, DDR5, LPDDR4,LPDDR5

(×32)
A5D 010 60 384 8 11 192 2 4 28
A5D 025 60 384 8 11 192 2 4 28
A5D 031 60 384 8 11 192 2 4 28
A5D 051 60 384 8 15 192 2 4 28
A5D 064 60 384 8 15 192 2 4 28
Table 6.  D-Series FPGA Family Plan—Transceivers and HPSThe values in this table are maximum resources or performance.
Device

Transceiver

28.1 Gbps Max. Rate

PCIe 4.0 Instance

10/25 Gigabit

Ethernet

(MAC & PCS)

 HPS
×4 ×8 Processor Cache Size
A5D 010 16 4 2 8
  • Dual core Arm* Cortex* -A76 up to 1.8 GHz
  • Dual core Arm* Cortex* -A55 up to 1.5 GHz
  • Shared: 2 MB L3
  • Cortex* -A76:
    • 64 KB L1
    • 256 KB L2
  • Cortex* -A55:
    • 32 KB L1
    • 128 KB L2
A5D 025 16 4 2 8
A5D 031 16 4 2 8
A5D 051 24 6 3 12
A5D 064 32 8 4 16
Related Information
7 Tera Operations Per Second
8 The fabric-feeding I/O PLL counts include the System PLL in the GTS transceiver banks. You can use the System PLL for core fabric usage if you do not use it for the transceiver.
Level Two Title