Intel Agilex® 5 FPGAs and SoCs Device Overview

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ID 762191
Date 9/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Intel Agilex® 5 FPGAs and SoCs 2. Intel Agilex® 5 FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel Agilex® 5 FPGAs and SoCs 5. Internal Embedded Memory in Intel Agilex® 5 FPGAs and SoCs 6. Variable-Precision DSP in Intel Agilex® 5 FPGAs and SoCs 7. Core Clock Network in Intel Agilex® 5 FPGAs and SoCs 8. General Purpose I/Os in Intel Agilex® 5 FPGAs and SoCs 9. I/O PLLs in Intel Agilex® 5 FPGAs and SoCs 10. External Memory Interface in Intel Agilex® 5 FPGAs and SoCs 11. Hard Processor System in Intel Agilex® 5 SoCs 12. Transceivers in Intel Agilex® 5 FPGAs and SoCs 13. MIPI* Protocols Support in Intel Agilex® 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Intel Agilex® 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Intel Agilex® 5 FPGAs and SoCs 16. Device Configuration and the SDM in Intel Agilex® 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Intel Agilex® 5 FPGAs and SoCs 18. Device Security for Intel Agilex® 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Intel Agilex® 5 FPGAs and SoCs 20. Power Management for Intel Agilex® 5 FPGAs and SoCs 21. Intel® Software and Tools for Intel Agilex® 5 FPGAs and SoCs 22. Revision History for the Intel Agilex® 5 FPGAs and SoCs Device Overview
1. Overview of the Intel Agilex® 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Intel Agilex® 5 FPGAs and SoCs 1.2. Intel Agilex® 5 FPGAs and SoCs Block Diagram 1.3. Intel Agilex® 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Intel Agilex® 5 SoCs
2. Intel Agilex® 5 FPGAs and SoCs Family Plan x
2.1. Intel Agilex® 5 FPGAs and SoCs D-Series 2.2. Intel Agilex® 5 FPGAs and SoCs E-Series 2.3. Intel Agilex® 5 FPGAs and SoCs Package Options
10. External Memory Interface in Intel Agilex® 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Intel Agilex® 5 FPGAs and SoCs x
12.1. PMA Features in Intel Agilex® 5 FPGA GTS Transceivers 12.2. PCS Features in Intel Agilex® 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Intel Agilex® 5 FPGAs and SoCs
1. Overview of the Intel Agilex® 5 FPGAs and SoCs
2. Intel Agilex® 5 FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex™ Core Architecture
4. Adaptive Logic Module in Intel Agilex® 5 FPGAs and SoCs
5. Internal Embedded Memory in Intel Agilex® 5 FPGAs and SoCs
6. Variable-Precision DSP in Intel Agilex® 5 FPGAs and SoCs
7. Core Clock Network in Intel Agilex® 5 FPGAs and SoCs
8. General Purpose I/Os in Intel Agilex® 5 FPGAs and SoCs
9. I/O PLLs in Intel Agilex® 5 FPGAs and SoCs
10. External Memory Interface in Intel Agilex® 5 FPGAs and SoCs
11. Hard Processor System in Intel Agilex® 5 SoCs
12. Transceivers in Intel Agilex® 5 FPGAs and SoCs
13. MIPI* Protocols Support in Intel Agilex® 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Intel Agilex® 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Intel Agilex® 5 FPGAs and SoCs
16. Device Configuration and the SDM in Intel Agilex® 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Intel Agilex® 5 FPGAs and SoCs
18. Device Security for Intel Agilex® 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Intel Agilex® 5 FPGAs and SoCs
20. Power Management for Intel Agilex® 5 FPGAs and SoCs
21. Intel® Software and Tools for Intel Agilex® 5 FPGAs and SoCs
22. Revision History for the Intel Agilex® 5 FPGAs and SoCs Device Overview
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7. Core Clock Network in Intel Agilex® 5 FPGAs and SoCs

Intel Agilex® 5 FPGAs and SoCs use programmable clock tree synthesis for its core clocking function.

Programmable clock tree synthesis uses dedicated clock tree routing and switching circuits. These dedicated circuits enable the Intel® Quartus® Prime software to create the exact clock trees that your design requires.

Advantages of using programmable clock tree synthesis:

  • Minimizes clock tree insertion delay
  • Reduces dynamic power dissipation in the clock tree
  • Allows greater flexibility of clocking in the core
  • Maintains backwards compatibility with legacy global and regional clocking schemes

Features of the core clock network of Intel Agilex® 5 FPGAs and SoCs:

  • Supports the second-generation Intel® Hyperflex™ core architecture
  • Supports the hard memory controllers13 for:
    • DDR4—up to 3,200 Mbps
    • DDR5—up to 4,000 Mbps
    • LPDDR4—up to 4,267 Mbps
    • LPDDR5—up to 4,267 Mbps
  • Supported by dedicated clock input pins and integer I/O PLLs
Related Information
13 Each Intel Agilex® 5 FPGA series has different hard memory controller support. For more information, refer to the related information.
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