Agilex™ 5 FPGAs and SoCs Device Overview

ID 762191
Date 4/01/2024
Document Table of Contents

7. Core Clock Network in Agilex™ 5 FPGAs and SoCs

Agilex™ 5 FPGAs and SoCs use programmable clock tree synthesis for its core clocking function.

Programmable clock tree synthesis uses dedicated clock tree routing and switching circuits. These dedicated circuits enable the Quartus® Prime software to create the exact clock trees that your design requires.

Advantages of using programmable clock tree synthesis:

  • Minimizes clock tree insertion delay
  • Reduces dynamic power dissipation in the clock tree
  • Allows greater flexibility of clocking in the core
  • Maintains backwards compatibility with legacy global and regional clocking schemes

Features of the core clock network of Agilex™ 5 FPGAs and SoCs:

  • Supports the second-generation Hyperflex® core architecture
  • Supports the hard memory controllers15 for:
    • DDR4—up to 3,200 Mbps
    • DDR5—up to 4,000 Mbps
    • LPDDR4—up to 4,267 Mbps
    • LPDDR5—up to 4,267 Mbps
  • Supported by dedicated clock input pins and integer I/O PLLs
15 Each Agilex™ 5 FPGA series has different hard memory controller support. For more information, refer to the related information.