AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents
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1. AN 738: Intel® Arria® 10 Device Design Guidelines

This document provides a set of design guidelines, recommendations, and a list of factors to consider for designs that use Intel® Arria® 10 devices. It is important to follow Intel® recommendations throughout the design process for high-density, high-performance Arria® 10 designs. This document also assists you with planning the FPGA and system early in the design process, which is crucial to successfully meet design requirements. For more information to help verify that you have followed each of the guidelines, use the “Design Checklist” topic in this app note.
Note: This application note does not include all Arria® 10 device details and features. For more information about Arria® 10 devices and features, refer to the " Intel® Arria® 10 Device Design Handbook".

The material references the Arria® 10 device architecture as well as aspects of the Quartus® Prime software and third-party tools that you might use in your design. The guidelines presented in this document can improve productivity and avoid common design pitfalls.

Table 1.  Summary of the Design Flow Stage and Guideline Topics
Stages of the Design Flow Guidelines
System Specification Planning design specifications, IP selection
Device Selection Device information, determining device variant and density, package offerings, migration, HardCopy ASICs, speed grade
Early System and Board Planning Early power estimation, thermal management option, planning for configuration scheme, planning for on-chip debugging
Pin Connection Considerations for Board Design Power-up, power pins, PLL connections, decoupling capacitors, configuration pins, signal integrity, board-level verification
I/O and Clock Planning Pin assignments, early pin planning, I/O features and connections, memory interfaces, clock and PLL selection, simultaneous switching noise (SSN)
Design Entry Coding styles and design recommendations, SOPC Builder, planning for hierarchical or team-based design
Design Implementation, Analysis, Optimization, and Verification Synthesis tool, device utilization, messages, timing constraints and analysis, area and timing optimization, compilation time, verification, power analysis and optimization
Figure 1.  Arria® 10 Device Design Flow