AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents Planning Design Partitions

Partitioning a design for an FPGA requires planning to ensure optimal results when the partitions are integrated and ensures that each partition is well placed, relative to other partitions in the device.

Follow Intel® ’s recommendations for creating design partitions to improve the overall quality of results. For example, registering partition I/O boundaries keeps critical timing paths inside one partition that can be optimized independently.

Plan your source code so that each design block is defined in a separate file. The software can automatically detect changes to each block separately. Use hierarchy in your design to provide more flexibility when partitioning. Keep your design logic in the leaves of the hierarchy trees; that is, the top level of the hierarchy should have very little logic, and the lower-level design blocks contain the logic.

Table 52.  Planning Design Partitions Checklist
Number Done? Checklist Item
1   Follow recommendations to set up your source code and partition your design for incremental compilation; plan early in the design flow.