AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents PLL and Transceiver Board Design Guidelines

Table 19.  PLL Board Design Guidelines Checklist
Number Done? Checklist Item
1   Connect all PLL power pins to reduce noise even if the design does not use all the PLLs.
2   Power supply nets should be provided by an isolated power plane, a power plane cut out, or thick trace of at least 20 mils.

Plan your board design when you design a power system for PLL usage and to minimize jitter, because PLLs contain analog components embedded in a digital device.