AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents Design Security Using Configuration Bitstream Encryption

The design security feature ensures that Arria® 10 designs are protected from copying, reverse engineering, and tampering. Arria® 10 devices have the ability to decrypt configuration bitstreams using the AES algorithm, an industry standard encryption algorithm that is FIPS-197 certified. Arria® 10 devices have a design security feature which utilizes a 256-bit security key.

The design security feature is available in the FPP, AS, or PS configuration schemes. The design security feature is not available in JTAG configuration scheme.

When the compression is turned on, the DCLK to DATA ratio changes accordingly based on the FPP configuration scheme selected (FPP ×8, FPP ×16, or FPP ×32). To ensure a successful configuration, the configuration controller must send the DCLK that meets the DCLK to DATA ratio.