1.1. System Specification
1.2. Device Selection
1.3. Early System and Board Planning
1.4. Pin Connection Considerations for Board Design
1.5. I/O and Clock Planning
1.6. Design Entry
1.7. Design Implementation, Analysis, Optimization, and Verification
1.8. Conclusion
1.9. Document Revision History
1.10. Design Checklist
1.11. Appendix: Arria® 10 Transceiver Design Guidelines
1.7.1. Selecting a Synthesis Tool
1.7.2. Device Resource Utilization Reports
1.7.3. Quartus Prime Messages
1.7.4. Timing Constraints and Analysis
1.7.5. Area and Timing Optimization
1.7.6. Preserving Performance and Reducing Compilation Time
1.7.7. Simulation
1.7.8. Formal Verification
1.7.9. Power Analysis
1.7.10. Power Optimization
1.3.4.1.2. Download Cables
The Quartus® Prime programmer supports configuration of the Arria® 10 devices directly using JTAG interfaces with Intel programming download cables. You can download design changes directly to the device with Intel download cables, making prototyping easy and enabling you to make multiple design iterations in quick succession. You can use the same download cable to program configuration devices on the board and use JTAG debugging tools such as the Signal Tap Embedded Logic Analyzer.
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