AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents

1.2.3. I/O Pin Count, LVDS Channels, and Package Offering

Arria® 10 devices are available in space-saving FineLine BGA packages with various I/O pin counts between 288 and 768 I/O pins. Determine the required number of I/O pins for your application, considering the design’s interface requirements with other system blocks.

Larger densities and package pin counts offer more full-duplex LVDS channels for different signaling; ensure that your device density-package combination includes enough LVDS channels. Other factors can also affect the number of I/O pins required for a design, including simultaneous switching noise (SSN) concerns, pin placement guidelines, pins used as dedicated inputs, I/O standard availability for each I/O bank, differences between I/O standards and speed for row and column I/O banks, and package migration options. For more information on choosing pin locations, refer to “Pin Connection Considerations for Board Design” and "I/O and Clock Planning"

You can compile any existing designs in the Quartus® Prime software to determine how many I/O pins are used. Also consider reserving I/O pins for debugging, as described in “Planning for On-Chip Debugging”.