AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents Selectable I/O Standards and Flexible I/O Banks

Arria® 10 I/O pins are arranged in groups called modular I/O banks. Depending on the device density, the number of I/O banks ranges from 6 to 16 banks, with up to eight I/O banks per side, depending on the device density.
Table 37.  Selectable Standards and Flexible I/O Banks Checklist
Number Done? Checklist Item
1   Select a suitable signaling type and I/O standard for each I/O pin. The I/O banks are located in I/O columns. Each I/O bank contains its own PLL, DPA, and SERDES circuitries.
2   Ensure that the appropriate I/O standard support is supported in the targeted I/O bank.
3   Place I/O pins that share voltage levels in the same I/O bank.
4   Verify that all output signals in each I/O bank are intended to drive out at the bank’s VCCIO voltage level.
5   Verify that all voltage-referenced signals in each I/O bank are intended to use the bank’s VREF voltage level.
6   Check the I/O bank support for LVDS and transceiver features.

Certain I/O banks on the top and bottom or left and right of the device support different I/O standards and voltage levels. You can assign I/O standards and make other I/O-related settings in the Pin Planner. Be sure to use the correct dedicated pin inputs for signals such as clocks and global control signals described in the Clock and PLL Selection section .

The board must supply each bank with one VCCIO voltage level for every VCCIO pin in a bank. Each I/O bank is powered by the VCCIO pins of that particular bank, and is independent of the VCCIO pins of other I/O banks. A single I/O bank supports output signals that are driving at the same voltage as the VCCIO. An I/O bank can simultaneously support any number of input signals with different I/O standards.

To accommodate voltage-referenced I/O standards, each I/O bank supports multiple VREF pins feeding a common VREF bus. Set the VREF pins to the correct voltage for the I/O standards in the bank. Each I/O bank can only have a single VCCIO voltage level and a single VREF voltage level at a given time. If the VREF pins are not used as voltage references, they cannot be used as generic I/O pins and should be tied to VCCIO of that same bank or GND.

An I/O bank including single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same VREF setting. Voltage-referenced bi-directional and output signals must drive out at the I/O bank’s VCCIO voltage level.

Different I/O banks include different support for LVDS signaling, and the Arria® 10 transceiver banks include additional support. There are two types of I/O banks, LVDS and 3 V.

The LVDS I/O bank supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination between the two pins. You can use each LVDS channel as transmitter or receiver.

The 3 V I/O bank supports only single-ended I/O standards up to 3 V. Each adjacent I/O pair also supports Differential SSTL and Differential HSTL I/O standards. The single-ended output of the 3 V I/O has the same set of features as the single-ended output of the DDR I/O IP, except the programmable pre-emphasis feature.

Refer to the Stratix V I/O banks figure that shows the location of each I/O bank and what each bank supports. The figures describing the number of I/Os in each bank provide bank information specific to each device density. Refer to the section describing I/O bank restrictions for information about which I/O standards can be combined in each bank, and the section describing I/O placement guidelines for details about LVDS restrictions.