AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents

1.5.1. Making FPGA Pin Assignments

Table 34.  Making FPGA Pin Assignments Checklist
Number Done? Checklist Item
1   Use the Quartus® Prime Pin Planner to make pin assignments.
2   Use Quartus® Prime Fitter messages and reports for sign-off of pin assignments.
3   Verify that the Quartus® Prime pin assignments match those in the schematic and board layout tools.

With the Quartus® Prime Pin Planner GUI, you can identify I/O banks, VREF groups, and differential pin pairings to help you through the I/O planning process. Right-click in the Pin Planner spreadsheet interface and click the Pin Finder to search for specific pins. If migration devices are selected, the Pin Migration view highlights pins that change function in the migration device when compared to the currently selected device.

You have the option of importing a Microsoft Excel spreadsheet into the Quartus® Prime software to start the I/O planning process if you normally use a spreadsheet in your design flow. You can also export a spreadsheet compatible (.csv) file containing your I/O assignments when all pins are assigned.

When you compile your design in the Quartus® Prime software, I/O Assignment Analysis in the Fitter validates that the assignments meet all the device requirements and generates messages if there are any problems.

Quartus® Prime designers can then pass the pin location information to PCB designers. Pin assignments between the Quartus® Prime software and your schematic and board layout tools must match to ensure the design works correctly on the board where it is placed, especially if changes to the pin-out must be made. The Pin Planner is integrated with certain PCB design EDA tools and can read pin location changes from these tools to check the suggested changes. When you compile your design, the Quartus® Prime software generates the .pin file. You can use this file to verify that each pin is correctly connected in the board schematics.