AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents Memory Interfaces

Table 38.  Memory Interfaces Checklist
Number Done? Checklist Item
1   Use the Arria® 10 External Memory Interfaces IP core for each memory interface, and follow connection guidelines/restrictions in the appropriate documentation.
2   For a given bank, most memory pins are tied to a dedicated location. Refer to the Arria® 10 GX and SX Device Family Pin Connection Guidelines for pin assignments.

Arria® 10 devices provide an efficient architecture to quickly and easily fit wide external memory interfaces with their small modular I/O banks. The Arria® 10 FPGA can support DDR external memory on any I/O banks on all sides of the device that do not support transceivers.

The self-calibrating Arria® 10 External Memory Interfaces IP core is optimized to take advantage of the Arria® 10 I/O structure. The Arria® 10 External Memory Interfaces IP core allows you to set external memory interface features and helps set up the physical interface (PHY) best suited for your system. When you use the Intel memory controller Intel FPGA IP functions, the Arria® 10 External Memory Interfaces IP core is instantiated automatically. If you design multiple memory interfaces into the device using Intel FPGA IP core, generate a unique interface for each instance to ensure good results instead of designing it once and instantiating it multiple times.

The data strobe DQS and data DQ pin locations are fixed in Arria® 10 devices. Before you design your device pin-out, refer to the memory interface guidelines for details and important restrictions related to the connections for these and other memory-related signals.

You can implement a protocol that is not supported by Arria® 10 External Memory Interfaces IP core by using the Altera PHYLite for Parallel Interfaces IP core.

Address and command pins within the address/command bank must follow a fixed pin-out scheme, as defined in the <variation_name>_readme.txt file generated with your IP core. The pin-out scheme varies according to the topology of the memory interface. The pin-out scheme is a hardware requirement that you must follow. Some schemes require three lanes to implement address and command pins, while others require four lanes.