AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents

1.9. Document Revision History

Table 65.  Document Revision History
Date Version Changes
June 2017 2017.06.30 Made the following changes:
  • Changed "EPCQ" to "EPCQ-L" globally.
  • Changed the description of the CLKUSR optional configuration pin to match the GUI in the "Quartus Prime Configuration Settings" section.
March 2017 2017.03.20 Minor formatting changes.
March 2017 2017.03.15 Rebranded as Intel.
July 2016 2.3 Made the following changes:
  • Changed the I/O pin counts in the “I/O Pin Count, LVDS Channels, and Package Offering” section.
  • Changed the transceiver speed grade availabilities in the “Speed Grade” section.
  • Updated the URLs to PCIe* documentation in the “PCIe” section.
  • Updated the URLs for Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide and DisplayPort IP Core User Guide in the “Transceiver Design Flow” section.
  • Updated the supported modes in the “Clock Feedback Mode” section.
  • Changed the minimum data rate in the “PCS Types Supported by GX Transceiver Channels” table.
  • Updated the URLs in the “Calibration” section.
  • Changed the transceiver speeds in the “Device Variants and Applications” table.
June 2016 2.2 Made the following changes:
  • Changed “28.3 Gbps” to “25.8 Gbps” globally.
  • Added the “GT Transceiver Bank Architecture for Bank GXBL1G” figure.
  • Added the “GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H” figure.
  • Changed the description in the “Simulation” section.
May 2016 2.1 Removed the step to select the Design Assistant option in the “Design Recommendations” section. The Design Assistant is not supported by Arria® 10 devices.
May 2015 2.0 Added further description for the requirement of CLKUSR in the “Optional Configuration Pins” section.

Changed “MegaWizard Plug-In Manager” to “IP Catalog” or “parameter editor” as appropriate, globally.

August 2014 1.0 Initial release.