AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents

1.11.6. Calibration

Arria 10 FPGA devices contain a dedicated calibration engine to compensate for process variations.

The calibration engine calibrates the analog portion of the transceiver to allow both the transmitter and receiver to operate at maximum performance. Each Arria 10 device contains two calibration engines and each engine resides on either side of the device. A hard NIOS II processor controls the calibration flow.

The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the CLKUSR clock must be free running and stable upon device power-up to successfully complete the calibration process and for optimal transceiver performance.