AN 738: Intel® Arria® 10 Device Design Guidelines

ID 683555
Date 6/30/2017
Document Table of Contents JTAG Pins

Table 22.  JTAG Pins Checklist
Number Done? Checklist Item
1   Connect JTAG pins to a stable voltage level if not in use.

Because JTAG configuration takes precedence over all other configuration methods, the JTAG pins should not be left floating or toggling during configuration if you do not use the JTAG interface. If you use the JTAG interface, follow the guidelines in this section.

JTAG Pin Connections

A device operating in JTAG mode uses four required pins—TDI, TDO, TMS, and TCK— and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have weak internal pull-up resistors. The JTAG output pin TDO and all JTAG input pins are powered by the 1.2 V, 1.5 V, and 1.8 V VCCPGM. All JTAG pins are tri-stated during JTAG reconfiguration. Do not drive voltage lower than 1.8 V, 1.5 V, and 1.2-V VCCPGM supply for the TDI, TMS, TCK, and TRST pins. The voltage supplies for TDI, TMS, TCK, and TRST input pins must be the same as set for the VCCPGM supply.

Table 23.  JTAG Pin Connections Checklist
Number Done? Checklist Item
1   Connect JTAG pins correctly to the download cable header. Ensure the pin order is not reversed.
2   To disable the JTAG state machine during power-up, pull the TCK pin low through a 1 kΩ resistor to ensure that an unexpected rising edge does not occur on TCK.
3   Pull TMS and TDI high through a 1 kΩ to 10 kΩ resistor.
4   Connect TRST directly to VCCPGM (Connecting the pin low disables the JTAG circuitry).

If you have more than one device in the chain, connect the TDO pin of a device to the TDI pin of the next device in the chain.

Noise on the JTAG pins during configuration, user mode, or power-up can cause the device to go into an undefined state or mode.

Download Cable Operating Voltage

The operating voltage supplied to the Intel download cable by the target board through the 10-pin header determines the operating voltage level of the download cable.

JTAG pins in the Arria® 10 device are powered up by VCCIO_SDM. In a JTAG chain containing devices with different VCCIO levels, ensure that the VIL max, VIH min, and the maximum VI specifications of the device JTAG input pins are not violated. Level shifter might be required between devices to meet the voltage specifications of the devices input pin.

Table 24.  Download Cable Operating Voltage Checklist
Number Done? Checklist Item
1   Ensure the download cable and JTAG pin voltages are compatible because the download cable interfaces with the JTAG pins of your device.

JTAG Signal Buffering

You might have to add buffers to a JTAG chain, depending on the JTAG signal integrity, especially the TCK signal, because it is the JTAG clock and the fastest switching JTAG signal. Intel recommends buffering the signals at the connector because cables and board connectors tend to make bad transmission lines and introduce noise to the signals. After this initial buffer at the connector, add buffers as the chain gets longer or whenever the signals cross a board connector.

If a cable drives three or more devices, buffer the JTAG signal at the cable connector to prevent signal deterioration. This also depends on the board layout, loads, connectors, jumpers, and switches on the board. Anything added to the board that affects the inductance or capacitance of the JTAG signals increases the likelihood that a buffer should be added to the chain.

Each buffer should drive no more than eight loads for the TCK and TMS signals, which drive in parallel. If jumpers or switches are added to the path, decrease the number of loads.

Table 25.  JTAG Signal Buffering Checklist
Number Done? Checklist Item
1   Buffer JTAG signals per the recommendations, especially for connectors or if the cable drives more than three devices.
2   If your device is in a configuration chain, ensure all devices in the chain are connected properly.