Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

Design Flow

Table 1.  Summary of the Design Flow Stage and Guideline Topics
Stages of the Design Flow Description
System Specification Planning design specifications, IP selection
Device Selection Device information, determining device variant and density, package offerings, migration, speed grade
Early System and Board Planning Power and thermal estimation, thermal management option, planning for configuration scheme, planning for on-chip debugging
Pin Connection Considerations for Board Design Power-up, power pins, PLL connections, decoupling capacitors, configuration pins, signal integrity, board-level verification
I/O and Clock Planning Pin assignments, early pin planning, I/O features and connections, memory interfaces, clock and PLL selection, simultaneous switching noise (SSN)
Design Entry Coding styles and design recommendations, Platform Designer, planning for hierarchical or team-based design
Design Implementation, Analysis, Optimization, and Verification Synthesis tool, device utilization, messages, timing constraints and analysis, area and timing optimization, compilation time, verification, power analysis and optimization
Figure 1.  Intel® Stratix® 10 Device Design Flow