Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Security Considerations Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Stratix® 10 Device Design Guidelines
Optional Configuration Pins
|1||Plan the board design to support optional configuration pins as required.|
You can enable the following optional configuration pins:
- OSC_CLK_1—Must be connected to a 25 MHz, 100 MHz, or 125 MHz source if used.
Intel® Stratix® 10 devices use OSC_CLK_1 pin as the reference clock for transceiver calibration. You must provide a stable and free running clock input at this pin.
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