Early Pin Planning and I/O Assignment Analysis
|Use the Create Top-Level Design File command with I/O Assignment Analysis to check the I/O assignments before the design is complete.
In many design environments, FPGA designers want to plan top-level FPGA I/O pins early so that board designers can start developing the PCB design and layout. The FPGA device I/O capabilities and board layout guidelines influence pin locations and other types of assignments. In cases where the board design team specifies an FPGA pin-out, it is crucial that you verify pin locations in the FPGA place-and-route software as soon as possible to avoid board design changes.
Starting FPGA pin planning early improves the confidence in early board layouts, reduces the chance of error, and improves the overall time to market for the design. You can create a preliminary pin-out for an Intel FPGA using the Intel® Quartus® Prime Pin Planner before the source code is designed.
Early in the design process, the system architect typically has information about the standard I/O interfaces (such as memory and bus interfaces), IP cores to be used in the design, and any other I/O-related assignments defined by system requirements.
The Pin Planner Create/Import IP Core feature interfaces with the IP catalog, and enables you to create or import custom IP cores that use I/O interfaces. Enter PLL and LVDS blocks, including options such as dynamic phase alignment (DPA), because options affect the pin placement rules. When you have entered as much I/O-related information as possible, generate a top-level design netlist file using the Create Top-Level Design File command in the Pin Planner. You can use the I/O analysis results to change pin assignments or IP parameters and repeat the checking process until the I/O interface meets your design requirements and passes the pin checks in the Intel® Quartus® Prime software.
When planning is complete, the preliminary pin location information can be passed to PCB designers. When the design is complete, use the reports and messages generated by the Intel® Quartus® Prime Fitter for the final sign-off of the pin assignments.