Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
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Device Power-Up

Table 26.  Device Power-Up Checklist
Number Done? Checklist Item
1   Design board for power-up: All Intel® Stratix® 10 GPIO pins are tri-stated until the device is configured and configuration pins drive out. The transceiver pins are at high impedance before the device periphery could get programmed. Once the periphery is programmed, the termination and Vcm are set immediately after transceiver calibration is complete.
2   Design voltage power supply ramps to be monotonic.
3   Set POR time to ensure power supplies are stable.
4   Design power sequencing and voltage regulators for best device reliability. Connect the GND between boards before connecting the power supplies.

The minimum current requirement for the power-on-reset (POR) supplies must be available during device power-up.

The Intel® Stratix® 10 device has Power-On Reset Circuitry, which keeps the device in a reset state until the power supply outputs are within the recommended operating range. The device must reach the recommended operating range within the maximum power supply ramp time. If the ramp time is not met, the device I/O pins and programming registers remain tri-stated and device configuration fails. For the Intel® Stratix® 10 device to exit POR, you must power the VCCBAT power supply even if you do not use the volatile key.

In Intel® Stratix® 10 devices, a pin-selectable option (MSEL) allows you to select between a typical POR time setting of 4 ms or 100 ms. In both cases, you can extend the POR time by using an external component to assert the nSTATUS pin low. Extend POR time if the board cannot meet the maximum power ramp time specifications to ensure the device configures properly and enters user mode.

Intel® Stratix® 10 devices have power-up sequencing and power-down sequencing requirements. You should consider the power-up timing and power-down timing for each rail in order to meet the power sequencing requirements.

Intel uses GND as a reference for I/O buffer designs. Connecting the GND between boards before connecting the power supplies prevents the GND on your board from being pulled up inadvertently by a path to power through other components on your board. A pulled-up GND could otherwise cause an out-of-specification I/O voltage or current condition with the Intel device.