Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

Clock and PLL Selection

Table 54.  Clock and PLL Selection Checklist
Number Done? Checklist Item
1   Use the correct dedicated clock pins and routing signals for clock and global control signals.
2   Use the device PLLs for clock management.
3   Analyze input and output routing connections for each PLL and clock pin. Ensure PLL inputs come from the dedicated clock pins or from another PLL.

The first stage in planning your clocking scheme is to determine your system clock requirements. Understand your device’s available clock resources and correspondingly plan the design clocking scheme. Consider your requirements for timing performance, and how much logic is driven by a particular clock.

Intel® Stratix® 10 devices provide dedicated low-skew and high fan-out routing networks.

The dedicated clock pins drive the clock network directly, ensuring lower skew than other I/O pins. Use the dedicated routing network to have a predictable delay with less skew for high fan-out signals. You can also use the clock pins and clock network to drive control signals like asynchronous reset.

Connect clock inputs to specific PLLs to drive specific low-skew routing networks. Analyze the global resource availability for each PLL and the PLL availability for each clock input pin.

Intel® Stratix® 10 devices contain dedicated resources for distributing signals throughout the fabric with balanced delay. These resources are typically used for clock signals. You can also use these resources for other signals with low-skew requirements. In Intel® Stratix® 10 devices, these resources are implemented as a programmable clock routing, which allows for the implementation of low-skew clock networks of variable size.

If your system requires more clock or control signals than are available in the target device, consider cases where the dedicated clock resource could be spared, particularly low fan-out and low-frequency signals where clock delay and clock skew do not have a significant impact on the design performance. Use the Global Signal assignment in the Intel® Quartus® Prime Assignment Editor to select the type of global routing, or set the assignment to Off to specify that the signal should not use any global routing resources.