Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Security Considerations Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Stratix® 10 Device Design Guidelines
Memory Power Reduction
|Reduce the number of memory clocking events.
Reduce the number of memory clocking events to reduce memory power consumption. You can use clock gating or the clock enable signals in the memory ports.