Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Public
Document Table of Contents

Configuration Pin Voltage Level

Table 32.  Configuration Pin Voltage Level Checklist
Number Done? Checklist Item
1   Ensure VCCIO_SDM and VCCIO of the configuration pins match the voltage level of the external devices used for configuration. When using the Avalon® -ST ×32 or ×16 configuration scheme, VCCIO of the I/O bank which the AVST_CLK, AVST_VALID, and AVST_DATA pins are located in, must match the VCCIO_SDM level.

Configuration pins from the Intel® Stratix® 10 device connect to external devices, for example the serial configuration device or Avalon® -ST host. The voltage level of the configuration pins need to match the voltage level of the devices connected to them. The JTAG and SDM I/Os used as configuration pins are powered by the VCCIO_SDM supply. For Avalon® -ST ×32 and ×16 configuration schemes, the AVST_CLK, AVST_VALID, and AVST_DATA pins are powered by the VCCIO of the I/O bank in which the pins reside in.