Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

PLLs and Clock Routing

Table 6.  PLLs and Clock Routing Checklist
Number Done? Checklist Item
1   Verify the number of PLLs and clock resources.

Verify that your chosen device density package combination includes enough PLLs and clock routing resources for your design.