Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

Configuration Features

Table 20.  Configuration Features Checklist
Number Done? Checklist Item
1   Ensure your configuration scheme and board support the required features: design security, remote upgrades, single event upset (SEU) mitigation.

This section describes Intel® Stratix® 10 configuration features and how they affect your design process.

Configuration Bitstream Compression

Configuration bitstream compression is always enabled in Intel® Stratix® 10 configuration. The Intel® Quartus® Prime software generates configuration files with compressed configuration data. This compressed file reduces the storage requirements in the configuration device or flash memory, and decreases the time required to transmit the configuration bitstream to the Intel® Stratix® 10 device.

Due to compressed configuration bitstream, passive configuration schemes for example Avalon® -ST ×8, ×16, and ×32 might require the external configuration host to pause sending configuration data by deasserting the AVST_READY signal.

Design Security Using Configuration Bitstream Encryption

The design security feature ensures that Intel® Stratix® 10 designs are protected from copying, reverse engineering, and tampering. Intel® Stratix® 10 devices have the ability to decrypt configuration bitstreams using the AES algorithm, an industry standard encryption algorithm that is FIPS-197 certified. Intel® Stratix® 10 devices have a design security feature which utilizes a 256-bit security key.

The design security feature is available in the all configuration schemes supported in the Intel® Stratix® 10 devices.

SEU Mitigation

Dedicated circuitry is built into Intel® Stratix® 10 devices for error detection and correction. When enabled, this feature checks for SEUs continuously and automatically. This allows you to confirm that the configuration data stored in an Intel® Stratix® 10 device is correct and alerts the system to a configuration error.

When using the SEU mitigation features, an SDM pin is used to implement the SEU_ERROR function. This pin flags errors for your system to take appropriate actions. Prior to compiling your design, enable the SEU_ERROR function and select an unused SDM pin to implement the SEU_ERROR function in the Intel® Quartus® Prime software.