Intel® Stratix® 10 Device Design Guidelines

ID 683738
Date 8/24/2022
Document Table of Contents

Memory Interfaces

Table 51.  Memory Interfaces Checklist
Number Done? Checklist Item
1   Use the External Memory Interfaces Intel Stratix 10 FPGA IP core for each memory interface, and follow connection guidelines/restrictions in the appropriate documentation.
2   Always check the pin table for the actual locations of the DQS and DQ pins and the EMIF pin table for locations of address and control pins.
3   I/O pins in banks 3A and 3D for Intel® Stratix® 10 TX 400 (1ST040E) do not support external memory interfaces. Do not use these I/O banks in this device to implement your external memory interface.

Intel® Stratix® 10 devices provide an efficient architecture to quickly and easily fit wide external memory interfaces with their small modular I/O banks. Any I/O banks that do not support transceiver operations in Intel® Stratix® 10 devices support external memory interfaces. However, DQS (data strobe or data clock) and DQ (data) pins are listed for EMIF supported banks in the device pin tables and are fixed at specific locations in the device. You must adhere to these pin locations to optimize routing, minimize skew, and maximize margins. Always check the pin table for the actual locations of the DQS and DQ pins and the EMIF pin table for locations of address and control pins.

Note: Maximum interface width varies from device to device depending on the number of I/O pins and DQS or DQ groups available. Achievable interface width also depends on the number of address and command pins that the design requires. To ensure adequate PLL, clock, and device routing resources are available, you should always test fit any IP in the Intel® Quartus® Prime software before PCB sign-off.

The self-calibrating External Memory Interfaces IP core is optimized to take advantage of the Intel® Stratix® 10 I/O structure. The External Memory Interfaces IP core allows you to set external memory interface features and helps set up the physical interface (PHY) best suited for your system. When you use the Intel memory controller Intel® FPGA IP functions, the External Memory Interfaces IP core is instantiated automatically. If you design multiple memory interfaces into the device using Intel FPGA IP core, generate a unique interface for each instance to ensure good results instead of designing it once and instantiating it multiple times.

The data strobe DQS and data DQ pin locations are fixed in Intel® Stratix® 10 devices. Before you design your device pin-out, refer to the memory interface guidelines for details and important restrictions related to the connections for these and other memory-related signals.

You can implement a protocol that is not supported by External Memory Interfaces IP core by using the PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core.

Address and command pins within the address/command bank must follow a fixed pin-out scheme, as defined in the <variation_name>_readme.txt file generated with your IP core. The pin-out scheme varies according to the topology of the memory interface. The pin-out scheme is a hardware requirement that you must follow. Some schemes require three lanes to implement address and command pins, while others require four lanes.

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